Electrical characteristics L9758
16/30 DocID14273 Rev 5
4.6 VCORE linear regulator
T
amb
= -40 °C to 125 °C, V
BAT
= V
BAT_SW
= 5.5 to 26.5 V, unless otherwise specified.
V
DDL_MAX
Maximum
overshoot
5 mA <I
DDL
< 1 A, V
PROG3
= Open
4.0 V < V
BAT_SW
< 18 V
ΔVB/Δt < 70 V/ms
5 mA < I
DDL
< 1 A, V
PROG3
= Low
4.0 V < V
BAT_SW
< 18 V
ΔVB/Δt < 70 V/ms
--
3.75
3.6
V
ΔV
DDL
/Δt
Output voltage
slew rate at power-
up
5 mA <I
DDL
< 1 A V
BAT_SW
=13.5 V 5 - 25 V/ms
I
DDL
Load current - 5 - 1000 mA
V
DDL
lineR Line regulation 5.5 V < V
BAT_SW
< 7 V -8 - +8 mV
V
DDL
loadR Load regulation 5 mA < I
DDL
< 1 A -8 - +8 mV
Table 11. VDDL linear regulator (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Table 12. VCORE linear regulator
Symbol Parameter Test condition Min. Typ. Max. Unit
V
CORE
Output voltage
5 mA < I
CORE
< 1 A;
4.0 V < V
BAT_SW
< 18 V
1.47 - 1.53 V
CddL
ESR
Output capacitor Ceramic or Tantalum
4.70
0
-
100
160
μF
mΩ
RRddL Ripple rejection F= 375 kHz 26 - - dB
V
CORE_M
Maximum
overshoot
5 mA < I
CORE
< 1 A
4.0 V < V
BAT_SW
< 18 V
- - 1.7 V
ΔV
CORE
/Δt
Output voltage
slew rate at power-
up
5 mA < I
CORE
< 1 A V
BAT_SW
=13.5 V 5 - 25 V/ms
I
CORE
Load current - 5 - 1000 mA
V
CORE_PROG
Range of
programmability
Using external resistor divider 1.05 1.5 2.8 V
V
CORE_FBK
Feedback voltage - 0.98 - 1.02 V
V
CORE
lineR Line regulation 5.5 V < V
BAT_SW
< 7 V -25 - +25 mV
V
CORE
loadR Load regulation 5 mA < I
CORE
< 1 A -25 - +25 mV
DocID14273 Rev 5 17/30
L9758 Electrical characteristics
29
4.7 VKAM linear regulator
T
amb
= -40 °C to 125 °C, V
BAT
= V
BAT_SW
= 5.5 to 26.5 V, unless otherwise specified.
4.8 VSTBY linear regulator
T
amb
= -40 °C to 125 °C, V
BAT
= V
BAT_SW
= 5.5 to 26.5 V, unless otherwise specified.
Table 13. VKAM linear regulator
Symbol Parameter Test condition Min. Typ. Max. Unit
V
KAM
Output voltage
0.1mA < I
VKAM
< 10mA, V
PROG1
= Low
4.0V < V
BAT
< 18V
0.1mA < I
VKAM
< 10mA, V
PROG1
=Open
4.0V < V
BAT
< 18V
0.9
1.37
-
1.1
1.65
V
C
VKAM
ESR
Output capacitor Ceramic
0.1
0
-
4.7
20
μF
mΩ
RR
VKAM
Ripple rejection F=375 kHz 26 - dB
V
KAM_M
Maximum overshoot
(absolute value
relative to GND)
0.1 mA < I
VKAM
< 10 mA, V
PROG1
= Low
4 V < V
BAT
< 18 V
0.1 mA < I
VKAM
< 10 mA, V
PROG1
= Open
4 V < V
BAT
< 18 V
--
1.2
1.7
V
Iddkamsh Current limit V
KAM
= 0.5 V 11 - 50 mA
I
KAM
Load current - 0.1 - 10 mA
V
KAM
lineR Line regulation 6 V < V
BAT
< 18 V -25 - +25 mV
V
KAM
loadR Load regulation 0.1 mA < I
KAM
< 10 mA -25 - +25 mV
Table 14. VSTBY linear regulator
Symbol Parameter Test condition Min. Typ. Max. Unit
V
STBY
Output voltage
0.1 mA < I
STBY
< 10 mA, V
PROG2
= Low
4 V < V
BAT
< 18 V
0.1 mA < I
STBY
< 10 mA, V
PROG2
= Open
4 V < V
BAT
< 18 V
2.47
3.13
-
2.73
3.47
V
C
STBY
ESR
Output capacitor Ceramic
0.1
0
-
10
20
μF
mΩ
RR
STBY
Ripple rejection F = 350 kHz 26 - - dB
V
STBY_M
Maximum overshoot
(absolute value
relative to GND)
0.1 mA < I
STBY
< 10 mA, V
PROG2
= Low
4 V < V
BAT
< 18 V
0.1 mA < I
STBY
< 10 mA, V
PROG2
= Open
4 V < V
BAT
< 18 V
--
3.05
3.75
V
I
STBY
sh Current limit V
STBY
= 0.5 V 11 - 50 mA
I
STBY
Load current - 0.1 - 10 mA
V
STBY
lineR Line regulation 6 V < V
BAT
<18 V -25 - +25 mV
V
STBY
loadR Load regulation 0.1 mA < I
STBY
< 10 mA -25 - +25 mV
Electrical characteristics L9758
18/30 DocID14273 Rev 5
4.9 VSA, VSB, VSC, VSD tracking linear regulator
T
amb
= -40 °C to 125 °C, V
BAT
= V
BAT_SW
= 5.5 to 26.5 V, unless otherwise specified.
4.10 RST5 and RSTL reset signals
T
amb
= -40 °C to 125 °C, V
BAT
= V
BAT_SW
= 5.5 to 26.5 V, unless otherwise specified.
Table 15. VSA, VSB, VSC, VSD tracking linear regulator
Symbol Parameter Test condition Min. Typ. Max. Unit
ΔV
TRK
Output voltage
tracking accuracy
1 mA < I
t1
< 50 mA, 6 V < V
BAT_SW
< 18 V
1 mA < I
t1
< 5 0mA, 4 V < V
BAT_SW
< 6 V
-7
-50
-
10
50
mV
I
TRK
sh Current limit V
tck
= 4.75 V 51 - 100 mA
C
TRK
ESR
Output load capacitor Ceramic or Tantalum
1
0
-
16
3
μF
mΩ
Ctckmin
ESRmin
Minimum output
capacitor for stability
Ceramic or Tantalum
1
0
-
3
μF
Ω
RR
TRK
Ripple rejection F= 375 kHz 26 - - dB
Vdrop Dropout voltage I
load
= 50 mA - - 300 mV
T
TSD
Thermal shutdown Vtck = 4.75 V (current limitation) 165 - 185 °C
T
HYST
Thermal hysteresis Vtck = 4.75 V (current limitation) 5 - 15 °C
I
TRK
Load current - 1 - 50 mA
Table 16. RST5 reset signals
Symbol Parameter Test condition Min. Typ. Max. Unit
I
RST5_H
Reset “high” leakage
current
V
RST5
= 5.15 V -3.0 - - μA
V
RST5_L
Reset “low” output
voltage
V
DD5
= 4.5 V Ire = 5 mA
V
DD5
= 1.0 V Ire = 1 mA
--
0.4
0.4
V
V
FTH_RST5
Reset threshold
decreasing
ΔV
DD5
/Δt < 0 4.5 -
V
DD5
0.2
V
V
RTH_RST5
Reset threshold
increasing
ΔV
DD5
/Δt > 0 4.5 -
V
DD5
0.07
V
V
HY_RST5
Reset threshold
hysteresis
-50--mV
t
ACT_RST5
Reset activation out
of tolerance duration
-15-25μs
t
DEL_RST5
Reset delay 4.7 kΩ < R
ext
< 47 kΩ 1 - 10 ms
t
ERR_RST5
Reset delay accuracy R
ext
±1% -15 - +15 %

L9758

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Power Management Specialized - PMIC Multiple output Volt Reg Engine Ctrl
Lifecycle:
New from this manufacturer.
Delivery:
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