LPC2131_32_34_36_38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5.1 — 29 July 2011 7 of 45
NXP Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Fig 4. LPC2134/36/38 LQFP64 pin configuration
LPC2134, LPC2134/01
LPC2136, LPC2136/01
LPC2138, LPC2138/01
P0.21/PWM5/AD1.6/CAP1.3 P1.20/TRACESYNC
P0.22/AD1.7/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2
RTCX1 P0.16/EINT0/MAT0.2/CAP0.2
P1.19/TRACEPKT3 P0.15/RI1/EINT2/AD1.5
RTCX2 P1.21/PIPESTAT0
V
SS
V
DD
V
DDA
V
SS
P1.18/TRACEPKT2 P0.14/DCD1/EINT1/SDA1
P0.25/AD0.4/AOUT P1.22/PIPESTAT1
P0.26/AD0.5 P0.13/DTR1/MAT1.1/AD1.4
P0.27/AD0.0/CAP0.1/MAT0.1 P0.12/DSR1/MAT1.0/AD1.3
P1.17/TRACEPKT1 P0.11/CTS1/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/RTS1/CAP1.0/AD1.2
P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3
P1.16/TRACEPKT0 P0.8/TXD1/PWM4/AD1.1
P0.31 P1.27/TDO
V
SS
VREF
P0.0/TXD0/PWM1 XTAL1
P1.31/TRST XTAL2
P0.1/RXD0/PWM3/EINT0 P1.28/TDI
P0.2/SCL0/CAP0.0 V
SSA
V
DD
P0.23
P1.26/RTCK RESET
V
SS
P1.29/TCK
P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3
P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2
P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3
P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS
P0.6/MOSI0/CAP0.2/AD1.0 V
DD
P0.7/SSEL0/PWM2/EINT2 V
SS
P1.24/TRACECLK VBAT
002aab407
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LPC2131_32_34_36_38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5.1 — 29 July 2011 8 of 45
NXP Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
AD1.7 to AD1.0 only available on LPC2134/36/38.
Fig 5. LPC2132/38 HVQFN64 pin configuration
002aab943
LPC2132/2138
Transparent top view
16 33
15 34
14 35
13 36
12 37
11 38
10 39
9 40
8 41
7 42
6 43
5 44
4 45
3 46
2 47
1 48
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
terminal 1
index area
P0.21/PWM5/AD1.6/CAP1.3
P0.22/AD1.7/CAP0.0/MAT0.0
RTCX1
P1.19/TRACEPKT3
RTCX2
V
SS
V
DDA
P1.18/TRACEPKT2
P0.25/AD0.4/AOUT
P0.26/AD0.5
P0.27/AD0.0/CAP0.1/MAT0.1
P1.17/TRACEPKT1
P0.28/AD0.1/CAP0.2/MAT0.2
P0.29/AD0.2/CAP0.3/MAT0.3
P0.30/AD0.3/EINT3/CAP0.0
P1.16/TRACEPKT0
P1.27/TDO
VREF
XTAL1
XTAL2
P1.28/TDI
V
SSA
P0.23
RESET
P1.29/TCK
P0.20/MAT1.3/SSEL1/EINT3
P0.19/MAT1.2/MOSI1/CAP1.2
P0.18/CAP1.3/MISO1/MAT1.3
P1.30/TMS
V
DD
V
SS
VBAT
P1.20/TRACESYNC
P0.17/CAP1.2/SCK1/MAT1.2
P0.16/EINT0/MAT0.2/CAP0.2
P0.15/RI1/EINT2/AD1.5
P1.21/PIPESTAT0
V
DD
V
SS
P0.14/DCD1/EINT1/SDA1
P1.22/PIPESTAT1
P0.13/DTR1/MAT1.1/AD1.4
P0.12/DSR1/MAT1.0/AD1.3
P0.11/CTS1/CAP1.1/SCL1
P1.23/PIPESTAT2
P0.10/RTS1/CAP1.0/AD1.2
P0.9/RXD1/PWM6/EINT3
P0.8/TXD1/PWM4/AD1.1
P0.31
V
SS
P0.0/TXD0/PWM1
P1.31/TRST
P0.1/RXD0/PWM3/EINT0
P0.2/SCL0/CAP0.0
V
DD
P1.26/RTCK
V
SS
P0.3/SDA0/MAT0.0/EINT1
P0.4/SCK0/CAP0.1/AD0.6
P1.25/EXTIN0
P0.5/MISO0/MAT0.1/AD0.7
P0.6/MOSI0/CAP0.2/AD1.0
P0.7/SSEL0/PWM2/EINT2
P1.24/TRACECLK
LPC2131_32_34_36_38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5.1 — 29 July 2011 9 of 45
NXP Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
5.2 Pin description
Table 3. Pin description
Symbol Pin Type Description
P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of
31 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while
P0.31 is output only pin. The operation of port 0 pins depends upon the pin function
selected via the pin connect block.
Pin P0.24 is not available.
P0.0/TXD0/
PWM1
19
[1]
O TXD0 — Transmitter output for UART0.
O PWM1 — Pulse Width Modulator output 1.
P0.1/RXD0/
PWM3/EINT0
21
[2]
I RXD0 — Receiver input for UART0.
O PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input.
P0.2/SCL0/
CAP0.0
22
[3]
I/O SCL0 — I
2
C0 clock input/output. Open drain output (for I
2
C-bus compliance).
I CAP0.0 — Capture input for Timer 0, channel 0.
P0.3/SDA0/
MAT0.0/EINT1
26
[3]
I/O SDA0 — I
2
C0 data input/output. Open drain output (for I
2
C-bus compliance).
O MAT0.0 — Match output for Timer 0, channel 0.
I EINT1 — External interrupt 1 input.
P0.4/SCK0/
CAP0.1/AD0.6
27
[4]
I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
I CAP0.1 — Capture input for Timer 0, channel 1.
I AD0.6 — ADC 0, input 6. This analog input is always connected to its pin.
P0.5/MISO0/
MAT0.1/AD0.7
29
[4]
I/O MISO0 — Master In Slave V
DD
= 3.6 V for SPI0. Data input to SPI master or data
output from SPI slave.
O MAT0.1 — Match output for Timer 0, channel 1.
I AD0.7 — ADC 0, input 7. This analog input is always connected to its pin.
P0.6/MOSI0/
CAP0.2/AD1.0
30
[4]
I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input to
SPI slave.
I CAP0.2 — Capture input for Timer 0, channel 2.
I AD1.0 — ADC 1, input 0. This analog input is always connected to its pin. Available in
LPC2134/36/38 only.
P0.7/SSEL0/
PWM2/EINT2
31
[2]
I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
O PWM2 — Pulse Width Modulator output 2.
I EINT2 — External interrupt 2 input.
P0.8/TXD1/
PWM4/AD1.1
33
[4]
O TXD1 — Transmitter output for UART1.
O PWM4 — Pulse Width Modulator output 4.
I AD1.1 — ADC 1, input 1. This analog input is always connected to its pin. Available in
LPC2134/36/38 only.
P0.9/RXD1/
PWM6/EINT3
34
[2]
I RXD1 — Receiver input for UART1.
O PWM6 — Pulse Width Modulator output 6.
I EINT3 — External interrupt 3 input.
P0.10/RTS1/
CAP1.0/AD1.2
35
[4]
O RTS1 — Request to Send output for UART1. Available in LPC2134/36/38.
I CAP1.0 — Capture input for Timer 1, channel 0.
I AD1.2 — ADC 1, input 2. This analog input is always connected to its pin. Available in
LPC2134/36/38 only.

LPC2131FBD64,151

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 32BIT 32KB FLASH 64LQFP
Lifecycle:
New from this manufacturer.
Delivery:
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