ASAHI KASEI [AK4114]
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Serial Control Interface
(1). 4-wire serial control mode (IIC= “L)
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C1-0 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MHz. PDN= “L resets the registers to their default values. When the state of
P/S pin is changed, the AK4114 should be reset by PDN= “L”.
CDTI
CCLK
CSN
C1
0 1234567
8 9 10 11 12 13 14 15
D4D5D6D7
A
1
A
2
A3
A
4R/WC0
A
0D0D1D2D3
CDTO
Hi-Z
WRITE
CDTI
C1 D4D5D6D7
A
1
A
2
A3
A
4R/WC0
A
0D0D1D2D3
CDTO
Hi-Z
READ
D4D5D6D7 D0D1D2D3
Hi-Z
C1-C0: Chip Address (Fixed to “00”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 34. 4-wire Serial Control I/F Timing
ASAHI KASEI [AK4114]
MS0098-E-04 2004/03
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(2). I
2
C bus control mode (IIC= “H”)
AK4114 supports the standard-mode I
2
C-bus (max : 100kHz). Then AK4114 can not be incorporated in a fast-mode
I
2
C-bus system (max : 400kHz).
(2)-1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4114
recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the
SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the
SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the
master device.
(2)-1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 35. Data transfer
(2)-1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
SCL
SDA
STOP CONDITIONSTART CONDITION
Figure 36. START and STOP conditions
ASAHI KASEI [AK4114]
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(2)-1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will
release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the
acknowledge clock pulse so that that it remains stable “L” during “H period of this clock pulse. The AK4114 will
generates an acknowledge after each byte has been received.
In the read mode, the slave, AK4114 will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP
condition.
SCL FROM
MASTER
acknowledge
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
1 98
START
CONDITION
Clock pulse
for acknowledge
not acknowledge
Figure 37. Acknowledge on the I
2
C-bus
(2)-1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If the
transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the
SDA line.
The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device
address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0
pin) set them. The eighth bit (LSB) of the first byte (R/W bit) defines whether a write or read condition is requested by
the master. A “1” indicates that the read operation is to be executed. A0” indicates that the write operation is to be
executed.
0 0 1 0 0 CAD1 CAD0 R/W
(Those CAD1/0 should match with CAD1/0 pins.)
Figure 38. The First Byte

AK4114VQ

Mfr. #:
Manufacturer:
Description:
IC AUDIO DECODER 24BIT 48LQFP
Lifecycle:
New from this manufacturer.
Delivery:
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