ASAHI KASEI [AK4114]
MS0098-E-04 2004/03
- 7 -
SWITCHING CHARACTERISTICS
(Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; C
L
=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz
External Clock Frequency
Duty
fECLK
dECLK
11.2896
40
50
24.576
60
MHz
%
MCKO1 Output Frequency
Duty
fMCK1
dMCK1
4.096
40
50
24.576
60
MHz
%
MCKO2 Output Frequency
Duty
fMCK2
dMCK2
2.048
40
50
24.576
60
MHz
%
PLL Clock Recover Frequency (RX0-7) fpll 32 - 192 kHz
LRCK Frequency
Duty Cycle
fs
dLCK
32
45
192
55
kHz
%
Audio Interface Timing
Slave Mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
(Note 6)
BICK
to LRCK Edge (Note 6)
LRCK to SDTO (MSB)
BICK
” to SDTO
DAUX Hold Time
DAUX Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRM
tBSD
tDXH
tDXS
80
30
30
20
20
20
20
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
Master Mode
BICK Frequency
BICK Duty
BICK” to LRCK
BICK” to SDTO
DAUX Hold Time
DAUX Setup Time
fBCK
dBCK
tMBLR
tBSD
tDXH
tDXS
-20
20
20
64fs
50
20
10
Hz
%
ns
ns
ns
ns
Control Interface Timing (4-wire serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “” to CCLK “
CCLK “” to CSN “
CDTO Delay
CSN “” to CDTO Hi-Z
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
150
50
50
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6. BICK rising edge must not occur at the same time as LRCK edge.
ASAHI KASEI [AK4114]
MS0098-E-04 2004/03
- 8 -
SWITCHING CHARACTERISTICS (Continued)
(Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; C
L
=20pF)
Parameter Symbol min typ max Units
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 7)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive load on bus
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
-
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.0
-
100
-
-
-
-
-
-
-
1000
300
-
400
kHz
µs
µs
µ
s
µ
s
µs
µs
ns
ns
ns
µ
s
pF
Reset Timing
PDN Pulse Width
tPW
150
ns
Note 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 8. I
2
C is a registered trademark of Philips Semiconductors.
Purchase of Asahi Kasei Microsystems Co., Ltd I
2
C components conveys a license under the Philips
I
2
C patent to use the components in the I
2
C system, provided the system conform to the I
2
C
specifications defined by Philips.
ASAHI KASEI [AK4114]
MS0098-E-04 2004/03
- 9 -
Timing Diagram
1/fECLK
tECLKL
VIH
tECLKH
XTI
VIL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
1/fMCK1
50%DVDDMCKO1
tMCKL1tMCKH1
dMCK1 = tMCKH1 x fMCK1 x 100
= tMCKL1 x fMCK1 x 100
1/fMCK2
50%DVDDMCKO2
tMCKL2tMCKH2
dMCK2 = tMCKH2 x fMCK2 x 100
= tMCKL2 x fMCK2 x 100
1/fs
LRCK
VIH
VIL
tLRLtLRH
dLCK = tLRH x fs x 100
= tLRL x fs x 100
Figure 1. Clock Timing
tLRB
LRCK
BICK
SDTO
tBSD
tBLR tBCKL tBCKH
tLRM
50%DVDD
DAUX
tDXS tDXH
VIH
VIL
VIH
VIL
VIH
VIL
tBCK
Figure 2. Serial Interface Timing (Slave Mode)

AK4114VQ

Mfr. #:
Manufacturer:
Description:
IC AUDIO DECODER 24BIT 48LQFP
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New from this manufacturer.
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