© Semiconductor Components Industries, LLC, 2014
January, 2018 − Rev. 20
1 Publication Order Number:
NBSG86A/D
NBSG86A
2.5V/3.3V SiGe Differential
Smart Gate with Output
Level Select
The NBSG86A is a multi−function differential Logic Gate which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm family of high
performance Silicon Germanium products. The device is housed in a
3 x 3 mm 16 pin QFN package.
Differential inputs incorporate internal 50 W termination resistors
and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The Output Level Select (OLS)
input is used to program the peak−to−peak output amplitude between
0 and 800 mV in five discrete steps.
The NBSG86A employs input default circuitry so that under open
input conditions (D
x
, D
x
, VTD
x
, VTD
x,
VTSEL) the outputs of the
device will remain stable.
Features
Maximum Input Clock Frequency > 8 GHz Typical
Maximum Input Data Rate > 8 Gb/s Typical
165 ps Typical Propagation Delay
40 ps Typical Rise and Fall Times
Selectable Swing PECL Output with Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
Selectable Output Level (0 V, 200 mV, 400 mV,
600 mV, or 800 mV Peak−to−Peak Output)
50 W Internal Input Termination Resistors
This is a Pb−Free Device
MARKING
DIAGRAM*
www.
onsemi.com
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
QFN16
MN SUFFIX
CASE 485G
1
See detailed ordering and shipping information on page 16 o
f
this data sheet.
ORDERING INFORMATION
16
SG
86A
ALYWG
G
1
NBSG86A
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2
VTD1 D1 D1
VTD1
VTD0 D0 D0 VTD0
V
EE
Q
Q
V
CC
OLS
SEL
SEL
VTSEL
5678
16 15 14 13
12
11
10
9
1
2
3
4
NBSG86A
Exposed Pad
(EP)
Figure 1. QFN16 Pinout (Top View)
Table 1. Pin Description
Pin Name I/O Description
1 OLS
(Note 3)
Input Input Pin for the Output Level Select (OLS). See Table 2.
2 SEL ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Select Logic Input.
3 SEL ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Select Logic Input.
4 VTSEL
Common Internal 50 W Termination Pin for SEL/SEL. See Table 7. (Note 1)
5 VTD1
Internal 50 W termination pin. See Table 7. (Note 1)
6 D1 ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Input 1. Internal 75 kW to V
EE
.
7 D1 ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Input 1. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
8 VTD1
Internal 50 W Termination Pin. See Table 7. (Note 1)
9 V
CC
Positive Supply Voltage (Note 2)
10 Q RSECL Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to V
TT
= V
CC
2 V.
11 Q RSECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
TT
= V
CC
− 2 V
12 V
EE
Negative Supply Voltage (Note 2)
13 VTD0
Internal 50 W Termination Pin. See Table 7. (Note 1)
14 D0 ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Input 0. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
15 D0 ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Input 0. Internal 75 kW to V
EE
.
16 VTD0
Internal 50 W Termination Pin. See Table 7. (Note 1)
EP The Exposed Pad (EP) and the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to the die but may be electrically and
thermally connected to V
EE
on the PC board.
1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage,
or left open, and if no signal is applied then the device will be susceptible to self−oscillation.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation.
3. When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, 2 kW resistor should be connected from OLS pin to V
EE
.
NBSG86A
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3
Table 2. OUTPUT LEVEL SELECT OLS
OLS Q/Q VPP OLS Sensitivity
V
CC
800 mV OLS − 75 mV
V
CC
− 0.4 V 200 mV OLS $ 150 mV
V
CC
− 0.8 V 600 mV OLS $ 100 mV
V
CC
− 1.2 V 0 OLS $ 75 mV
V
EE
(Note 4) 400 mV OLS $ 100 mV
Float 600 mV N/A
4. When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, 2.0 kW resistor should be
connected from OLS to V
EE
.
Figure 2. Logic Diagram
D0
Q
SEL
VTD0
Q
SEL
VTD0
50 W
50 W
D0
D1
VTD1
VTD1
50 W
50 W
D1
50 W
50 W
VTSEL
R
1
R
2
R
1
R
1
R
2
R
1
V
EE
V
CC
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50 W
VTD1
VTD1
50 W
50 W
50 W
50 W
VTSEL
Figure 3. Configuration for AND/NAND Function
V
CC
VT or
V
BB
b
D0
D0
D1
D1
Table 3. AND/NAND TRUTH TABLE (Note 5)
b * b
D0 D1 SEL Q
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
5. D0, D1, SEL are inverse of D0, D1, SEL unless specified other-
wise.

NBSG86AMNHTBG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates BBG SIGE DIF SMRTGTE OUTPUT LEVEL
Lifecycle:
New from this manufacturer.
Delivery:
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