NBSG86A
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14
APPLICATION INFORMATION
All NBSG86A inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential
input signal (LVDS, PECL, or CML) are minimum input swing of 75 mV and the maximum input swing of 2500 mV. Within
these conditions, the input voltage can range from V
CC
to 1.2 V. Examples interfaces are illustrated below in a 50 W
environment (Z = 50 W). For output termination and interface, refer to application note AND8020/D.
Table 14. INTERFACING OPTIONS
Interfacing Options Connections
CML Connect VTD and VTD to V
CC
(See Figure 18)
LVDS Connect VTD and VTD Together (See Figure 20)
AC−COUPLED Bias VTD and VTD Inputs within Common Mode Range (V
CMR
) (See Figure 19)
RSECL, PECL, NECL Standard ECL Termination Techniques (See Figure 22)
LVTTL, LVCMOS An External Voltage (V
THR
) should be Applied to the Unused Complementary Differential Input. Nominal
V
THR
is 1.5 V for LVTTL and V
CC
/ 2 for LVCMOS Inputs. This Voltage must be within the
V
THR
Specification. (See Figure 21)
50 W
V
CC
D
D
50 W
NBSG86A
V
CC
VTD
V
EE
V
CC
Q
50 W 50 W
CML
Driver
V
EE
Figure 18. CML Interface
Q
Z = 50 W
Figure 19. PECL Interface
50 W
V
CC
V
CC
PECL
Driver
D
D
50 W
NBSG86A
V
EE
V
Bias
*
VTD
V
EE
R
T
R
T
V
EE
V
CC
R
T
5.0 V
290 W
3.3 V
150 W
2.5 V
80 W
Recommended R
T
Values
VTD
V
CC
VTD
V
Bias
*
Z = 50 W
Z = 50 W
Z = 50 W
C
C
*V
Bias
must be within common mode range limits (V
CMR
)
