PCA85276 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 9 April 2015 28 of 55
NXP Semiconductors
PCA85276
Automotive 40 x 4 LCD driver
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered)
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition
Acknowledgement on the I
2
C-bus is illustrated in Figure 19.
Fig 18. System configuration
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Fig 19. Acknowledgement of the I
2
C-bus
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PCA85276 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 9 April 2015 29 of 55
NXP Semiconductors
PCA85276
Automotive 40 x 4 LCD driver
8.5 I
2
C-bus controller
The PCA85276 acts as an I
2
C-bus slave receiver. It does not initiate I
2
C-bus transfers or
transmit data to an I
2
C-bus master receiver. The only data output from the PCA85276 are
the acknowledge signals of the selected devices. Device selection depends on the
I
2
C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0 and A1 are normally
tied to V
SS
which defines the hardware subaddress 0. In multiple device applications A0
and A1 are tied to V
SS
or V
DD
using a binary coding scheme, so that no two devices with a
common I
2
C-bus slave address have the same hardware subaddress.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I
2
C-bus protocol
Two I
2
C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCA85276. The entire I
2
C-bus slave address byte is shown in Table 17.
The PCA85276 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte that a PCA85276 will respond to,
is defined by the level tied to its SA0 input (V
SS
for logic 0 and V
DD
for logic 1).
Having two reserved slave addresses allows the following on the same I
2
C-bus:
Up to 8 PCA85276 for very large LCD applications
The use of two types of LCD multiplex drive modes
The I
2
C-bus protocol is shown in Figure 20. The sequence is initiated with a START
condition (S) from the I
2
C-bus master which is followed by one of the two possible
PCA85276 slave addresses available. All PCA85276 whose SA0 inputs correspond to
bit 0 of the slave address respond by asserting an acknowledge in parallel. This I
2
C-bus
transfer is ignored by all PCA85276 whose SA0 inputs are set to the alternative level.
Table 17. I
2
C slave address byte
Slave address
Bit 7 6 5 4 3 2 1 0
MSB LSB
011100SA0R/W
PCA85276 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 9 April 2015 30 of 55
NXP Semiconductors
PCA85276
Automotive 40 x 4 LCD driver
After an acknowledgement, one or more command bytes follow that define the status of
each addressed PCA85276.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C (see Figure 21
). The command bytes are also acknowledged by all addressed
PCA85276 on the bus.
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data directed to the intended PCA85276 device.
An acknowledgement after each byte is asserted only by the PCA85276 that are
addressed via address lines A0 and A1. After the last display byte, the I
2
C-bus master
asserts a STOP condition (P). Alternately a START may be asserted to restart an I
2
C-bus
access.
Fig 20. I
2
C-bus protocol
Fig 21. Format of command byte
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PCA85276ATT/AJ

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers Automotive LCD drvr low multiplex
Lifecycle:
New from this manufacturer.
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