PCA85276 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 9 April 2015 35 of 55
NXP Semiconductors
PCA85276
Automotive 40 x 4 LCD driver
13. Dynamic characteristics
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] Not tested in production.
Table 20. Dynamic characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 8.0 V; T
amb
=
40
C to +105
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock
f
clk(int)
internal clock frequency
[1]
3505 4800 6240 Hz
f
clk(ext)
external clock frequency 960 - 6720 Hz
f
fr
frame frequency internal clock 146 200 260 Hz
external clock 40 - 280 Hz
t
clk(H)
HIGH-level clock time 60 - - s
t
clk(L)
LOW-level clock time 60 - - s
Synchronization
t
PD(SYNC_N)
SYNC propagation delay - 30 - ns
t
SYNC_NL
SYNC LOW time 1 - - s
t
PD(drv)
driver propagation delay V
LCD
= 5 V
[2]
--30s
I
2
C-bus
[3]
Pin SCL
f
SCL
SCL clock frequency - - 400 kHz
t
LOW
LOW period of the SCL
clock
1.3 - - s
t
HIGH
HIGH period of the SCL
clock
0.6 - - s
Pin SDA
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
Pins SCL and SDA
t
BUF
bus free time between a
STOP and START
condition
1.3 - - s
t
SU;STO
set-up time for STOP
condition
0.6 - - s
t
HD;STA
hold time (repeated)
START condition
0.6 - - s
t
SU;STA
set-up time for a repeated
START condition
0.6 - - s
t
r
rise time of both SDA and
SCL signals
f
SCL
= 400 kHz - - 0.3 s
f
SCL
< 125 kHz - - 1.0 s
t
f
fall time of both SDA and
SCL signals
--0.3s
C
b
capacitive load for each
bus line
--400pF
t
w(spike)
spike pulse width on the I
2
C-bus - - 50 ns
