Address Mapping to DRAM
Address Mirroring
To achieve optimum routing of the address bus on DDR4 multi rank modules, the ad-
dress bus will be wired as shown in the table below, or mirrored. For quad rank mod-
ules, ranks 1 and 3 are mirrored and ranks 0 and 2 are non-mirrored. Highlighted ad-
dress pins have no secondary functions allowing for normal operation when cross-
wired. Data is still read from the same address it was written. However, Load Mode op-
erations require a specific address. This requires the controller to accommodate for a
rank that is "mirrored." Systems may reference DDR4 SPD to determine if the module
has mirroring implemented or not. See the JEDEC DDR4 SPD specification for more de-
tails.
Table 9: Address Mirroring
Edge Connector Pin DRAM Pin, Non-mirrored DRAM Pin, Mirrored
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A4
A4 A4 A3
A5 A5 A6
A6 A6 A5
A7 A7 A8
A8 A8 A7
A9 A9 A9
A10 A10 A10
A11 A11 A13
A13 A13 A11
A12 A12 A12
A14 A14 A14
A15 A15 A15
A16 A16 A16
A17 A17 A17
BA0 BA0 BA1
BA1 BA1 BA0
BG0 BG0 BG1
BG1 BG1 BG0
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Address Mapping to DRAM
09005aef861e841e
asf18c2gx72hz.pdf – Rev. F 8/16 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Temperature Sensor with SPD EEPROM Operation
Thermal Sensor Operations
The integrated thermal sensor continuously monitors the temperature of the module
PCB directly below the device and updates the temperature data register. Temperature
data may be read from the bus host at any time, which provides the host real-time feed-
back of the module's temperature. Multiple programmable and read-only temperature
registers can be used to create a custom temperature-sensing solution based on system
requirements and JEDEC JC-42.2.
EVENT_n Pin
The temperature sensor also adds the EVENT_n pin (open-drain), which requires a pull-
up to V
DDSPD
. EVENT_n is a temperature sensor output used to flag critical events that
can be set up in the sensor’s configuration registers. EVENT_n is not used by the serial
presence-detect (SPD) EEPROM.
EVENT_n has three defined modes of operation: interrupt, comparator, and TCRIT. In
interrupt mode, the EVENT_n pin remains asserted until it is released by writing a 1 to
the clear event bit in the status register. In comparator mode, the EVENT_n pin clears
itself when the error condition is removed. Comparator mode is always used when the
temperature is compared against the TCRIT limit. In TCRIT only mode, the EVENT_n
pin is only asserted if the measured temperature exceeds the TCRIT limit; it then re-
mains asserted until the temperature drops below the TCRIT limit minus the TCRIT
hysteresis.
SPD EEPROM Operation
DDR4 SDRAM modules incorporate SPD. The SPD data is stored in a 512-byte, JEDEC
JC-42.4-compliant EEPROM that is segregated into four 128-byte, write-protectable
blocks. The SPD content is aligned with these blocks as shown in the table below.
Block Range Description
0 0–127 000h–07Fh Configuration and DRAM parameters
1 128–255 080h–0FFh Module parameters
2 256–319 100h–13Fh Reserved (all bytes coded as 00h)
320–383 140h–17Fh Manufacturing information
3 384–511 180h–1FFh End-user programmable
The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45,
"Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining
128 bytes of storage are available for use by the customer.
The EEPROM resides on a two-wire I
2
C serial interface and is not integrated with the
memory bus in any manner. It operates as a slave device in the I
2
C bus protocol, with all
operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achieva-
ble at 2.5V (NOM).
Micron implements reversible software write protection on DDR4 SDRAM-based mod-
ules. This prevents the lower 384 bytes (bytes 0 to 383) from being inadvertently pro-
grammed or corrupted. The upper 128 bytes remain available for customer use and are
unprotected.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Temperature Sensor with SPD EEPROM Operation
09005aef861e841e
asf18c2gx72hz.pdf – Rev. F 8/16 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.
Table 10: Absolute Maximum Ratings
Symbol Parameter Min Max Units Notes
V
DD
V
DD
supply voltage relative to V
SS
–0.4 1.5 V 1
V
DDQ
V
DDQ
supply voltage relative to V
SS
–0.4 1.5 V 1
V
PP
Voltage on V
PP
pin relative to V
SS
–0.4 3.0 V 2
V
IN
, V
OUT
Voltage on any pin relative to V
SS
–0.4 1.5 V
Table 11: Operating Conditions
Symbol Parameter Min Nom Max Units Notes
V
DD
V
DD
supply voltage 1.14 1.2 1.26 V 1
V
PP
DRAM activating power supply 2.375 2.5 2.75 V 2
V
REFCA(DC)
Input reference voltage command/
address bus
0.49 × V
DD
0.5 × V
DD
0.51 × V
DD
V 3
I
VTT
Termination reference current from V
TT
–500 500 mA
V
TT
Termination reference voltage (DC) –
command/address bus
0.49 × V
DD
-
20mV
0.5 × V
DD
0.51 × V
DD
+
20mV
V 4
I
IN
Input leakage current; any input excluding ZQ;
0V < V
IN
< 1.1V
–2.0 2.0 µA 5
I
I/O
DQ leakage; 0V < V
in
< V
DD
–4.0 4.0 µA 5
I
ZQ
Input leakage current; ZQ –3.0 3.0 µA 5, 6
I
OZpd
Output leakage current; V
OUT
= V
DD
; DQ is disabled 5.0 µA
I
OZpu
Output leakage current; V
OUT
=V
SS
; DQ and ODT are
disabled; ODT is disabled with ODT input HIGH
5.0 µA
I
VREFCA
V
REFCA
leakage; V
REFCA
= V
DD
/2 (after DRAM is ini-
tialized)
–2.0 2.0 µA 5
Notes:
1. V
DDQ
tracks with V
DD
; V
DDQ
and V
DD
are tied together.
2. V
PP
must be greater than or equal to V
DD
at all times.
3. V
REFCA
must not be greater than 0.6 x V
DD
. When V
DD
is less than 500mV, V
REF
may be
less than or equal to 300mV.
4. V
TT
termination voltages in excess of the specification limit adversely affect the voltage
margins of command and address signals and reduce timing margins.
5. Multiply by the number of DRAM die on the module.
6. Tied to ground. Not connected to edge connector.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Electrical Specifications
09005aef861e841e
asf18c2gx72hz.pdf – Rev. F 8/16 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.

MTA18ASF2G72HZ-2G6D1

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Description:
IC SDRAM DDR
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