AD9743BCPZRL Datasheet AD9747BCPZ, AD9746BCPZ, AD9745BCPZ | P19-P21

Data Sheet AD9741/AD9743/AD9745/AD9746/AD9747

Rev. A | Page 19 of 28

internally by the serial port controller by decrementing from

the specified address. For LSB-first format, the specified address

is a beginning address or the least significant address in the

current cycle. Remaining register addresses for multiple byte

data transfers are generated internally by the serial port

controller by incrementing from the specified address.

MSB/LSB TRANSFERS

The serial port can support both MSB-first and LSB-first data

formats. This functionality is controlled by Register 0x00, Bit 6.

The default is Logic 0, which is MSB-first format.

When using MSB-first format (LSBFIRST = 0), the instruction

and data bit must be written from MSB to LSB. Multibyte data

transfers in MSB-first format start with an instruction byte that

includes the register address of the most significant data byte.

Subsequent data bytes are loaded into sequentially lower

address locations. In MSB-first mode, the serial port internal

address generator decrements for each byte of the multibyte

data transfer.

When using LSB-first format (LSBFIRST = 1), the instruction

and data bit must be written from LSB to MSB. Multibyte data

transfers in LSB-first format start with an instruction byte that

includes the register address of the least significant data byte.

Subsequent data bytes are loaded into sequentially higher

address locations. In LSB-first mode, the serial port internal

address generator increments for each byte of the multibyte

data transfer.

Use of a single-byte transfer when changing the serial port data

format is recommended to prevent unexpected device behavior.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

Chip Select Bar (CSB)

Active low input starts and gates a communication cycle. It

allows more than one device to be used on the same serial

communication lines. CSB must stay low during the entire

communication cycle. Incomplete data transfers are aborted

anytime the CSB pin goes high. SDO and SDIO pins go to a

high impedance state when this input is high.

Serial Clock (SCLK)

The serial clock pin is used to synchronize data to and from the

device and to run the internal state machines. The maximum

frequency of SCLK is 40 MHz. All data input is registered on

the rising edge of SCLK. All data is driven out on the falling

edge of SCLK.

Serial Data I/O (SDIO)

Data is always written into the device on this pin. However,

SDIO can also function as a bidirectional data output line.

The configuration of this pin is controlled by Register 0x00,

Bit 7. The default is Logic 0, which configures the SDIO pin

as unidirectional.

Serial Data Out (SDO)

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. The configuration of this

pin is controlled by Register 0x00, Bit 7. If this bit is set to a

Logic 1, the SDO pin does not output data and is set to a high

impedance state.

R/W N1 N0 A4 A3 A2 A1 A0 D7 D6

D7 D6

INSTRUCTION

CYCLE D

A TRANSFER

CYCLE

CSB

SCLK

SDIO

SDO

06569-014

Figure 23. Serial Register Interface—MSB First

A0 A1 A2 A3 A4 N0 N1 R/W D0

INSTRUCTION CYCLE

DATA

TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

06569-015

Figure 24. Serial Register Interface Timing—LSB First

INSTRUCTION BIT 6INSTRUCTION

BIT 7

CSB

SCLK

SDIO

PWH

PWL

SCLK

–1

06569-016

Figure 25. Timing Diagram for SPI Register Write

DATA

BIT N – 1DATA BIT N

CSB

SCLK

SDIO

SDO

06569-017

Figure 26. Timing Diagram for SPI Register Read

AD9741/AD9743/AD9745/AD9746/AD9747 Data Sheet

Rev. A | Page 20 of 28

SPI REGISTER MAP

Reading any register returns previously written values for all defined register bits, unless otherwise noted. Change serial port configu-

ration or execute software reset in single byte instruction only to avoid unexpected device behavior.

Table 14.

SPI Control 0x00 0x00 SDIODIR LSBFIRST SWRESET

Data Control 0x02 0x00 DATTYPE

ONEPORT

INVDCO

Power Down 0x03 0x00 PD_DCO PD_AUX2 PD_AUX1 PD_BIAS PC_CLK PD_DAC2 PD_DAC1

DAC Mode Select 0x0A 0x00 DAC1MOD<1:0> DAC2MOD<1:0>

DAC1 Gain LSB 0x0B 0xF9 DAC1FSC<7:0>

DAC1 Gain MSB 0x0C 0x01 DAC1FSC<9:8>

AUX DAC1 LSB 0x0D 0x00 AUXDAC1<7:0>

AUX DAC1 MSB 0x0E 0x00 AUX1PIN AUX1DIR AUXDAC1<9:8>

DAC2 Gain LSB 0x0F 0xF9 DAC2FSC<7:0>

DAC2 Gain MSB 0x10 0x01 DAC2FSC<9:8>

AUX DAC2 LSB 0x11 0x00 AUXDAC2<7:0>

AUX DAC2 MSB 0x12 0x00 AUX2PIN AUX2DIR AUXDAC2<9:8>

Data Sheet AD9741/AD9743/AD9745/AD9746/AD9747

Rev. A | Page 21 of 28

SPI REGISTER DESCRIPTIONS

Table 15.

SPI Control 0x00 7 SDIODIR 0, operate SPI in 4-wire mode, SDIO pin operates as an input only

1, operate SPI in 3-wire mode, SDIO pin operates as a bidirectional I/O line

6 LSBFIRST 0, LSBFIRST off, SPI serial data mode is MSB to LSB

1, LSBFIRST on, SPI serial data mode is LSB to MSB

5 SWRESET 0, resume normal operation following software RESET

1, software RESET; loads default values to all registers (except Register 0x00)

Data Control 0x02 7 DAT TYPE 0, DAC input data is twos complement binary format

1, DAC input data is unsigned binary format

6 ONEPORT 0, normal two port input mode

1, optional single port input mode, interleaved data received on Port 1 only

4 INVDCO 1, inverts data clock output signal

Power Down 0x03 7 PD_DCO 1, power down data clock output

5 PD_AUX2 1, power down AUX2 DAC

4 PD_AUX1 1, power down AUX1 DAC

3 PD_BIAS 1, power down reference voltage bias circuit

2 PD_CLK 1, power down DAC clock input circuit

1 PD_DAC2 1, power down DAC2 analog output

0 PD_DAC1 1, power down DAC1 analog output

DAC Mode Select

0x0A

3:2

DAC1MOD<1:0>

00, selects normal mode, DAC1

01, selects mix mode, DAC1

10, selects return-to-zero mode, DAC1

1:0

DAC2MOD<1:0>

00, selects normal mode, DAC2

01, selects mix mode, DAC2

10, selects return-to-zero mode, DAC2

DAC1 Gain

0x0B

7:0

DAC1FSC<7:0>

DAC1 full-scale 10-bit adjustment word

0x0C 1:0 DAC1FSC<9:8> 0x03FF, sets full-scale current to the maximum value of 31.66 mA

0x01F9, sets full-scale current to the nominal value of 20.0 mA

0x0000, sets full-scale current to the minimum value of 8.64 mA

AUX DAC1 0x0D 7:0 AUXDAC1<7:0> Auxiliary DAC1 10-bit output current adjustment word

0x0E 1:0 AUXDAC1<9:8> 0x03FF, sets output current magnitude to 2.0 mA

0x0200, sets output current magnitude to 1.0 mA

0x0000, sets output current magnitude to 0.0 mA

7 AUX1PIN 1, AUX1P output pin is active

0, AUX1N output pin is active

6 AUX1DIR 0, configures AUX1 DAC output to source current

1, configures AUX1 DAC output to sink current

DAC2 Gain 0x0F 7:0 DAC2FSC<7:0> DAC2 full-scale 10-bit adjustment word

0x10 1:0 DAC2FSC<9:8> 0x03FF, sets full-scale current to the maximum value of 31.66 mA

0x01F9, sets full-scale current to the nominal value of 20.0 mA

0x0000, sets full-scale current to the minimum value of 8.64 mA

AUX DAC2 0x11 7:0 AUXDAC2<7:0> Auxiliary DAC2 10-bit output current adjustment word

0x12 1:0 AUXDAC2<9:8> 0x03FF, sets output current magnitude to 2.0 mA

0x0200, sets output current to 1.0 mA

0x0000, sets output current to 0.0 mA

7 AUX2PIN 1, AUX2P output pin is active

0, AUX2N output pin is active

AUX2DIR

0, configures AUX2 DAC output to source current

1, configures AUX2 DAC output to sink current

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

AD9743BCPZRL

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC Dual 10-Bit 250 MSPS

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AD9743BCPZRL

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