AD9743BCPZRL Datasheet AD9747BCPZ, AD9746BCPZ, AD9745BCPZ | P22-P24

AD9741/AD9743/AD9745/AD9746/AD9747 Data Sheet

Rev. A | Page 22 of 28

DIGITAL INPUTS AND OUTPUTS

The AD9741/AD9743/AD9745/AD9746/AD9747 can operate

in two data input modes: dual-port mode and single-port mode.

For the default dual-port mode (ONEPORT = 0), each DAC

receives data from a dedicated input port. In single-port mode

(ONEPORT = 1), however, both DACs receive data from Port 1.

In single-port mode, DAC1 and DAC2 data is interleaved and

the IQSEL input is used to steer data to the correct DAC.

In single-port mode, when the IQSEL input is high, Port 1

data is delivered to DAC1 and when IQSEL is low, Port 1 data

is delivered to DAC2. The IQSEL input should always coincide

and be time-aligned with the other data bus signals. In single-

port mode, minimum setup and hold times apply to the IQSEL

input as well as to the input data signals. In dual-port mode, the

IQSEL input is ignored.

In dual-port mode, the data must be delivered at the sample rate

(up to 250 MSPS). In single-port mode, data must be delivered

at twice the sample rate. Because the data inputs function only

up to 250 MSPS, it is only practical to operate the DAC clock at

up to 125 MHz in single-port mode.

In both dual-port and single-port modes, a data clock output

(DCO) signal is available as a fixed time base with which to

stimulate data from an FPGA. This output signal always

operates at the sample rate. It may be inverted by asserting

the INVDCO bit.

INPUT DATA TIMING

With most DACs, signal-to-noise ratio (SNR) is a function of

the relationship between the position of the clock edges and the

point in time at which the input data changes. The AD9741/

AD9743/AD9745/AD9746/AD9747 are rising edge triggered

and thus exhibit greater SNR sensitivity when the data tran-

sition is close to this edge.

The specified minimum setup and hold times define a window

of time, within each data period, where the data is sampled

correctly. Generally, users should position data to arrive

relative to the DAC clock and well beyond the minimum

setup and minimum hold times. This becomes increasingly

more important at increasingly higher sample rates.

DUAL-PORT MODE TIMING

The timing diagram for the dual-port mode is shown in

Figure 27.

CLKP/CLKN

DCO

P1D<15:0>

P2D<15:0>

DCO

DBH

DBS

06569-018

Q3 Q4

Figure 27. Data Interface Timing, Dual-Port Mode

In Figure 27, data samples for DAC1 are labeled Ix and data

samples for DAC2 are labeled Qx. Note that the differential

DAC clock input is shown in a logical sense (CLKP/CLKN).

The data clock output is labeled DCO.

Setup and hold times are referenced to the positive transition of

the DAC clock. Data should arrive at the input pins such that

the minimum setup and hold times are met. Note that the data

clock output has a fixed time delay from the DAC clock and

may be a more convenient signal to use to confirm timing.

SINGLE-PORT MODE TIMING

The single-port mode timing diagram is shown in Figure 28.

06569-019

CLKP/CLKN

DCO

P1D<15:0>

IQSEL

DBS

DBH

DCO

I1 Q1 I2 Q2

Figure 28. Data Interface Timing, Single-Port Mode

In single-port mode, data for both DACs is received on the

Port 1 input bus. Ix and Qx data samples are interleaved and

arrive twice as fast as in dual-port mode. Accompanying the

data is the IQSEL input signal, which steers incoming data to its

respective DAC. When IQSEL is high, data is steered to DAC1

and when IQSEL is low, data is steered to DAC2. IQSEL should

coincide as well as be time-aligned with incoming data.

SPI PORT, RESET, AND PIN MODE

In general, when the AD9741/AD9743/AD9745/AD9746/

AD9747 are powered up, an active high pulse applied to the

RESET pin should follow. This insures the default state of all

control register bits. In addition, once the RESET pin goes low,

the SPI port can be activated, so CSB should be held high.

For applications without a controller, the AD9741/AD9743/

AD9745/AD9746/AD9747 also support pin mode operation,

which allows some functional options to be pin, selected with-

out the use of the SPI port. Pin mode is enabled anytime the

RESET pin is held high. In pin mode, the four SPI port pins

take on secondary functions, as shown in Tabl e 16.

Table 16. SPI Pin Functions (Pin Mode)

Pin Name Pin Mode Description

SCLK

ONEPORT (Register 0x02, Bit 6), bit value (1/0)

equals pin state (high/low)

SDIO

DATTYPE (Register 0x02, Bit 7), bit value (1/0)

equals pin state (high/low)

CSB

Enable Mix Mode, if CSB is high, Register 0x0A

is set to 0x05 putting both DAC1 and DAC2 into

mix mode

SDO

Enable full power-down, if SDO is high, Register

0x03 is set to 0xFF

Data Sheet AD9741/AD9743/AD9745/AD9746/AD9747

Rev. A | Page 23 of 28

In pin mode, all register bits are reset to their default values

with the exception of those that are controlled by the SPI pins.

Note also that the RESET pin should be allowed to float and

must be pulled low. Connect an external 10 kΩ resistor to

DVSS. This avoids unexpected behavior in noisy environments.

DRIVING THE DAC CLOCK INPUT

The DAC clock input requires a low jitter drive signal. It is a

PMOS differential pair powered from the CVDD18 supply.

Each pin can safely swing up to 800 mV p-p at a common-

mode voltage of about 400 mV. Though these levels are not

directly LVDS-compatible, CLKP and CLKN can be driven by

an ac-coupled, dc-offset LVDS signal, as shown in Figure 29.

LVDS_P_IN CLKP

50Ω

0.1µF

LVDS_N_IN CLKN

= 400mV

06569-021

Figure 29. LVDS DAC Clock Drive Circuit

Using a CMOS or TTL clock is also acceptable for lower sample

rates. It can be routed through an LVDS translator and then

ac-coupled as described previously, or alternatively, it can be

transformer-coupled and clamped, as shown in Figure 30.

50Ω

TTL OR CMOS

CLK INPUT

CLKP

CLKN

= 400mV

BAV99ZXCT

HIGH SPEED

DUAL DIODE

0.1µF

06569-022

Figure 30. TTL or CMOS DAC Clock Drive Circuit

If a sine wave signal is available, it can be transformer-coupled

directly to the DAC clock inputs, as shown in Figure 31.

50Ω

SINE WA

INPUT

CLKP

CLKN

= 400mV

06569-034

Figure 31. Sine Wave DAC Clock Drive Circuit

The 400 mV common-mode bias voltage can be derived from

the CVDD18 supply through a simple divider network, as

shown in Figure 32.

0.1µF 1nF

= 400mV

CVDD18

CVSS

1kΩ

287Ω

06569-023

Figure 32. DAC Clock VCM Circuit

It is important to use CVDD18 and CVSS for any clock bias

circuit as noise that is coupled onto the clock from another

power supply is multiplied by the DAC input signal and

degrades performance.

FULL-SCALE CURRENT GENERATION

The full-scale currents on DAC1 and DAC2 are functions of

the current drawn through an external resistor connected to

the FSADJ pin (Pin 54). The required value for this resistor is

10 kΩ. An internal amplifier sets the current through the

resistor to force a voltage equal to the band gap voltage of 1.2 V.

This develops a reference current in the resistor of 120 μA.

CURRENT

SCALING

1.2V BANDGAP

DAC1 GAIN

DAC2 GAIN

AD9747

DAC1

DAC2

DAC FULL SCALE

REFERENCE CURRENT

REFIO

FSADJ

0.1µF

10kΩ

06569-024

Figure 33. Reference Circuitry

REFIO (Pin 55) should be bypassed to ground with a 0.1 μF

capacitor. The band gap voltage is present on this pin and can

be buffered for use in external circuitry. The typical output

impedance is near 5 kΩ. If desired, an external reference can

be connected to REFIO to overdrive the internal reference.

Internal current mirrors provide a means for adjusting the

DAC full-scale currents. The gain for DAC1 and DAC2 can be

adjusted independently by writing to the DAC1FSC<9:0> and

DAC2FSC<9:0> register bits. The default value of 0x01F9 for

the DAC gain registers gives an I

of 20 mA, where I

equals

























×+×= FSCDACI

10,000

V 1.2

The full-scale output current range is 8.6 mA to 31.7 mA for

06569-025

(mA)

0 256 512

768

1024

DAC GAIN CODE

Figure 34. I

vs. DAC Gain Code

AD9741/AD9743/AD9745/AD9746/AD9747 Data Sheet

Rev. A | Page 24 of 28

DAC TRANSFER FUNCTION

Each DAC output of the AD9741/AD9743/AD9745/AD9746/

AD9747 drives complementary current outputs I

OUTP

and I

OUTN

OUTP

provides a near full-scale current output (I

) when all bits

are high. For example,

DAC CODE = 2

− 1

where:

N = 8-/10-/12-/14-/16-bits (for AD9741/AD9743/AD9745/

AD9746/AD9747 respectively), and I

OUTN

provides no current.

The current output appearing at I

OUTP

and I

OUTN

is a function of

both the input code and I

and can be expressed as

OUTP

= (DAC DATA/2

) × I

(1)

OUTN

= ((2

− 1) − DAC DATA)/2

× I

(2)

where DAC DATA = 0 to 2

− 1 (decimal representation).

The two current outputs typically drive a resistive load directly

or via a transformer. If dc coupling is required, I

OUTP

and I

OUTN

should be connected to matching resistive loads (R

LOAD

) that are

tied to analog common (AVSS). The single-ended voltage

output appearing at the I

OUTP

and I

OUTN

pins is

OUTP

= I

OUTP

× R

LOAD

(3)

OUTN

= I

OUTN

× R

LOAD

(4)

Note that to achieve the maximum output compliance of 1 V at

the nominal 20 mA output current, R

LOAD

must be set to 50 Ω.

Also note that the full-scale value of V

OUTP

and V

OUTN

should

not exceed the specified output compliance range to maintain

specified distortion and linearity performance.

There are two distinct advantages to operating the AD9741/

AD9743/AD9745/AD9746/AD9747 differentially. First, differ-

ential operation helps cancel common-mode error sources

associated with I

OUTP

and I

OUTN

, such as noise, distortion, and

dc offsets. Second, the differential code dependent current

and subsequent output voltage (V

DIFF

) is twice the value of the

single-ended voltage output (V

OUTP

or V

OUTN

), providing 2×

signal power to the load.

DIFF

= (I

OUTP

– I

OUTN

) × R

LOAD

(5)

ANALOG MODES OF OPERATION

The AD9741/AD9743/AD9745/AD9746/AD9747 utilize a

proprietary quad-switch architecture that lowers the distortion

of the DAC output by eliminating a code dependent glitch that

occurs with conventional dual-switch architectures. But whereas

this architecture eliminates the code dependent glitches, it creates

a constant glitch at a rate of 2 × f

DAC

. For communications

systems and other applications requiring good frequency

domain performance, this is seldom problematic.

The quad-switch architecture also supports two additional

modes of operation; mix mode and return-to-zero (RZ) mode.

The waveforms of these two modes are shown in Figure 35. In

mix mode, the output is inverted every other half clock cycle.

This effectively chops the DAC output at the sample rate. This

chopping has the effect of frequency shifting the sinc roll-off

from dc to f

DAC

. Additionally, there is a second subtle effect on

the output spectrum. The shifted spectrum is shaped by a second

sinc function with a first null at 2 × f

DAC

. The reason for this

shaping is that the data is not continuously varying at twice the

clock rate, but is simply repeated.

In RZ mode, the output is set to midscale on every other half

clock cycle. The output is similar to the DAC output in normal

mode except that the output pulses are half the width and half

the area. Because the output pulses have half the width, the

sinc function is scaled in frequency by 2 and has a first null at

2 × f

DAC

. Because the area of the pulses is half that of the pulses

in normal mode, the output power is half the normal mode

output power.

INPUT DATA

DAC CLK

4-SWITCH

DAC OUTPUT

(

MIX MODE)

4-SWITCH

DAC OUTPUT

(RETURN TO

ZERO MODE)

06569-026

Figure 35. Mix Mode and RZ Mode DAC Waveforms

The functions that shape the output spectrums for normal mode,

mix mode, and RZ mode, are shown in Figure 36. Switching

between the modes reshapes the sinc roll off inherent at the

DAC output. This ability to change modes in the AD9741/

AD9743/AD9745/AD9746/AD9747 makes the parts suitable for

direct IF applications. The user can place a carrier anywhere in

the first three Nyquist zones depending on the operating mode

selected. The performance and maximum amplitude in all three

zones are impacted by this sinc roll off depending on where the

carrier is placed, as shown in Figure 36.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

AD9743BCPZRL

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC Dual 10-Bit 250 MSPS

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