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AD9743BCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
Data Sheet AD9741/AD9743/AD9745/AD9746/AD9747
Rev. A | Page 7 of 28
DIGITAL AND TIMING SPECIFICATIONS
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
FS
= 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 5. AD9741/AD9743/AD9745/AD9746/AD9747
Parameter Min Typ Max Unit
DAC CLOCK INPUTS (CLKP, CLKN)
Differential Peak-to-Peak Voltage 400 800 1600 mV
Single-Ended Peak-to-Peak Voltage 800 mV
Common-Mode Voltage 300 400 500 mV
Input Current
1
μA
Input Frequency 250 MHz
DATA CLOCK OUTPUT (DCO)
Output Voltage High
2.4
V
Output Voltage Low 0.4 V
Output Current 10 mA
DAC Clock to Data Clock Output Delay (t
DCO
) 2.0 2.2 2.8 ns
DATA PORT INPUTS
Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current 1 μA
Data to DAC Clock Setup Time (t
DBS
Dual-Port Mode) 400 ps
Data to DAC Clock Hold Time (t
DBH
Dual-Port Mode) 1200 ps
DAC Clock to Analog Output Data Latency (Dual-Port Mode) 7 Cycles
Data or IQSEL Input to DAC Clock Setup Time (t
DBS
Single-Port Mode) 400 ps
Data or IQSEL Input to DAC Clock Hold Time (t
DBH
Single-Port Mode) 1200 ps
DAC Clock to Analog Output Data Latency (Single-Port Mode) 8 Cycles
SERIAL PERIPHERAL INTERFACE
SCLK Frequency (f
SCLK
) 40 MHz
SCLK Pulse Width High (t
PWH
) 10 ns
SCLK Pulse Width Low (t
PWL
)
10
ns
CSB to SCLK Setup Time (t
S
) 1 ns
CSB to SCLK Hold Time (t
H
) 0 ns
SDIO to SCLK Setup Time (t
DS
) 1 ns
SDIO to SCLK Hold Time (t
DH
) 0 ns
SCLK to SDIO/SDO Data Valid Time (t
DV
) 1 ns
RESET Pulse Width High 10 ns
WAKE-UP TIME AND OUTPUT LATENCY
From DAC Outputs Disabled 200 μs
From Full Device Power-Down 1200 μs
DAC Clock to Analog Output Latency (Dual-Port Mode) 7 Cycles
DAC Clock to Analog Output Latency (Single-Port Mode) 8 Cycles
AD9741/AD9743/AD9745/AD9746/AD9747 Data Sheet
Rev. A | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
With
Respect to
Rating
AVDD33, DVDD33 AVSS DVSS
CVSS
−0.3 V to +3.6 V
DVDD18, CVDD18 AVSS DVSS
CVSS
−0.3 V to +1.98 V
AVSS DVSS CVSS −0.3 V to +0.3 V
DVSS AVSS CVSS −0.3 V to +0.3 V
CVSS AVSS DVSS −0.3 V to +0.3 V
REFIO AVSS −0.3 V to AVDD33 + 0.3 V
IOUT1P, IOUT1N, IOUT2P,
IOUT2P, AUX1P, AUX1N,
AUX2P, AUX2N
AVSS −1.0 V to AVDD33 + 0.3 V
P1D15 to P1D0,
P2D15 to P2D0
DVSS −0.3 V to DVDD33 + 0.3 V
CLKP, CLKN CVSS −0.3 V to CVDD18 + 0.3 V
RESET, CSB, SCLK, SDIO, SDO DVSS –0.3 V to DVDD33 + 0.3 V
Junction Temperature 125°C
Storage Temperature −65°C to +150°C
THERMAL RESISTANCE
Thermal resistance tested using JEDEC standard 4-layer
thermal test board with no airflow.
Table 7.
Package Type θ
JA
Unit
CP-72-1 (Exposed Pad Soldered to PCB) 25 °C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet AD9741/AD9743/AD9745/AD9746/AD9747
Rev. A | Page 9 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CVDD18
CVSS
CLK
P
CLKN
CVSS
CVDD18
DVSS
DVDD18
P1D7
P1D6
P1D5
P1D4
P1D3
P1D2
P1D1
P1D0
17NC
18NC
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
NC
NC
NC
NC
NC
NC
DCO
NC
DVDD33
DVSS
IQSEL
NC
P2D7
P2D6
P2D5
P2D4
35
P2D3
36
P2D2
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FSADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
NC
NC
NC
NC
NC
NC
NC
NC
P2D0
P2D1
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
A
VSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
AVSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
AVDD33
AVDD33
REFIO
NC = NO CONNECT
06569-006
PIN 1
INDIC
A
T
OR
AD9741
(T
O
P VIEW)
Figure 2. AD9741 Pin Configuration
Table 8. AD9741 Pin Function Descriptions
Pin No. Mnemonic Description
1, 6
CVDD18
Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Common (0 V).
3 CLKP Differential DAC Clock Input.
4 CLKN Complementary Differential DAC Clock Input.
7, 28, 48 DVSS Digital Supply Common (0 V).
8, 47 DVDD18 Digital Core Supply Voltage (1.8 V).
9 to 16 P1D<7:0> Port 1 Data Bit Inputs.
17 to 24, 26, 30, 39 to 46 NC No Connect.
25 DCO Data Clock Output. Use to clock data source.
27 DVDD33 Digital I/O Supply Voltage (3.3 V).
29 IQSEL I/Q Framing Signal for Single-Port Mode Operation.
31 to 38
P2D<7:0>
Port 2 Data Bit Inputs.
49 SDO Serial Peripheral Interface Data Output.
50 SDIO Serial Peripheral Interface Data Input and Optional Data Output.
51 SCLK Serial Peripheral Interface Clock Input.
52 CSB Serial Peripheral Interface Chip Select Input. Active low.
53 RESET Hardware Reset. Active high.
54
FSADJ
Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS.
55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS.
56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V).
59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1.
60
IOUT2N
DAC2 Current Output Complement. Sources full-scale current when data bits are all 0.
62 AUX2P Auxiliary DAC2 Default Current Output Pin.
63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI.
65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI.
66 AUX1P Auxiliary DAC1 Default Current Output Pin.
68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0.
69
IOUT1P
DAC1 Current Output. Sources full-scale current when data bits are all 1.
EPAD AVSS
Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical
stability and must be electrically tied to low impedance GND plane for low noise performance.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

AD9743BCPZRL

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Buy AD9743BCPZRL
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Dual 10-Bit 250 MSPS
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