DS1557 4Meg, Nonvolatile, Y2K-Compliant Timekeeping RAM
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DATA WRITE MODE
The DS1557 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of t
WR
prior to the initiation of a subsequent
read or write cycle. Data in must be valid t
DS prior to the end of the write and remain valid for t
DH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs t
WEZ
after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written and read only when V
CC
is greater than V
PF
.
However, when V
CC
is below the power-fail point V
PF
(point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When V
CC
falls below the battery switch
point V
SO
(battery supply level), device power is switched from the V
CC
pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to nominal
levels.
The 3.3V device is fully accessible and data can be written and read only when V
CC
is greater than V
PF
.
When V
CC
falls below V
PF
, access to the device is inhibited. If V
PF
is less than V
SO
, the device power is
switched from V
CC
to the internal backup lithium battery when V
CC
drops below V
PF
. If V
PF
is greater
than V
SO
, the device power is switched from V
CC
to the internal backup lithium battery when V
CC
drops
below V
SO
. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to
nominal levels.
All control, data, and address signals must be powered down when V
CC
is powered down.
BATTERY LONGEVITY
The DS1557 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the V
CC
supply is not present. The capability of this internal power
supply is sufficient to power the DS1557 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25C with the internal clock
oscillator running in the absence of V
CC
.
INTERNAL BATTERY MONITOR
The DS1557 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF)
bit of the Flags Register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are
questionable.
POWER-ON RESET
A temperature compensated comparator circuit monitors the level of V
CC
. When V
CC
falls to the power
fail trip point, the RST signal (open drain) is pulled low. When V
CC
returns to nominal levels, the RST
signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
