SC18IS600IPW/S8HP Datasheet SC18IS600IPW/S8HP, SC18IS600IBS,157, SC18IS600IPW,128 | P10-P12

Product data sheet Rev. 7.1 — 20 November 2017 10 of 30

NXP Semiconductors

SC18IS600

SPI to I

C-bus interface

6.2.6 I

C-bus status register (I2CStat)

This register reports the results of I

C-bus transmit and receive transaction between

SC18IS600 and an I

C-bus slave device.

Table 9. I

C-bus status

value

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I

C-bus status description

0xF0 11110000Transmission successful. The SC18IS600 has

successfully completed an I

C-bus read or write

transaction. An interrupt is generated on INT

. This

is also the default status after reset. No interrupt is

generated after reset.

0xF1 11110001I

C-bus device address not acknowledged. No

C-bus slave device has acknowledged the slave

address that has been sent out in an I

C-bus read

or write transaction. An interrupt is generated on

INT

0xF2 11110010I

C-bus device address not acknowledged. An

C-bus slave has not acknowledged the byte that

has just been transmitted by the SC18IS600. An

interrupt is generated on INT

0xF3 11110011I

C-bus busy. The SC18IS600 is busy performing

an I

C-bus transaction, no new transaction should

be initiated by the host. No interrupt is generated.

0xF8 11111000I

C-bus time-out (see Section 6.2.5 “I

C-bus

time-out register (I2CTO)”). The SC18IS600 has

started an I

C-bus transaction that has taken

longer than the time programmed in I2CTO

unsuccessful arbitration or when an I

C-bus slave

is (continuously) pulling the SCL clock LOW. An

interrupt is generated on INT

0xF9 11111001I

C-bus invalid data count. The number of bytes

specified in a read or write command to the

SC18IS600. An interrupt is generated on INT

Product data sheet Rev. 7.1 — 20 November 2017 11 of 30

NXP Semiconductors

SC18IS600

SPI to I

C-bus interface

6.3 I

C-bus serial interface

C-bus uses two wires (SDA and SCL) to transfer information between devices

connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi-master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I

C-bus may be used for test and diagnostic purposes.

A typical I

C-bus configuration is shown in Figure 9. The SC18IS600 device provides a

byte-oriented I

C-bus interface that supports data transfers up to 400 kHz. (Refer to

UM10204, “I

C-bus specification and user manual”.)

6.4 Serial Peripheral Interface (SPI)

The host communicates with the SC18IS600 via the SPI interface. The SC18IS600

operates in Slave mode up to 3 Mbit/s.

The SPI interface has four pins: SCLK, MOSI, MISO, and CS

• SCLK, MOSI and MISO are typically tied together between two or more SPI devices.

Data flows from the master to the SC18IS600 on the MOSI (Master Out Slave In) pin

and flows from SC18IS600 to the master on the MISO (Master In Slave Out) pin. The

SCLK signal is an input to the SC18IS600.

• CS is the slave select pin. In a typical configuration, an SPI master selects one SPI

device as the current slave. An SPI slave device uses its CS

pin to determine whether

it is selected.

Typical connections are shown in Figure 10

Fig 9. I

C-bus configuration

002aab716

SC18IS600

C-BUS

DEVICE

C-BUS

DEVICE

C-bus

SDA

SCL

Product data sheet Rev. 7.1 — 20 November 2017 12 of 30

NXP Semiconductors

SC18IS600

SPI to I

C-bus interface

6.5 SPI message format

6.5.1 Write N bytes to I

C-bus slave device

The SPI host issues the write command by sending a 0x00 command followed by the total

number of bytes (maximum 96 bytes excluding the address) to send and an I

C-bus slave

device address followed by I

C-bus data bytes, beginning with the first byte (data byte 1)

and ending with the last byte (data byte N). Once the SPI host issues this command, the

SC18IS600 will access the I

C-bus slave device and start sending the I

C-bus data bytes.

When the I

C-bus write transaction has successfully finished, and interrupt is generated

on the INT

pin, and the ‘transaction completed’ status can be read in I2CStat.

Note that the third byte sent by the host is the device I

C-bus slave address. The

SC18IS600 will ignore the least significant bit so a write will always be performed even if

the least significant bit is a ‘1’.

Fig 10. SPI single master multiple slaves configuration

002aab717

master

MISO

MOSI

SPICLK

PORT

slave

SCLK

SC18IS600

slave

SCLK

OTHER SPI

DEVICE

Fig 11. Write N bytes to I

C-bus slave device

002aab718

NUMBER

OF BYTES

0x00

COMMAND

SLAVE ADDRESS

+ W

SPI host sends

DATA

BYTE 1

DATA

BYTE N

SCLK

MOSI

data byte 1 data byte N0slave address A[7:1]number of bytes D[7:0]command 0x00

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

SC18IS600IPW/S8HP

Mfr. #:

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Manufacturer:

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Description:

I/O Controller Interface IC SPI to I2C-bus Interface

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