SC18IS600IPW/S8HP Datasheet SC18IS600IPW/S8HP, SC18IS600IBS,157, SC18IS600IPW,128 | P7-P9

Product data sheet Rev. 7.1 — 20 November 2017 7 of 30

NXP Semiconductors

SC18IS600

SPI to I

C-bus interface

6.2.1.2 Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down

transistor of the pin when the pin latch contains a logic 0. To be used as a logic output, a

pin configured in this manner must have an external pull-up, typically a resistor tied to

. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open-drain pin configuration is shown in Figure 5

An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.

6.2.1.3 Input-only configuration

The input-only pin configuration is shown in Figure 6

. It is a Schmitt-triggered input that

also has a glitch suppression circuit.

Fig 4. Quasi-bidirectional output configuration

002aab882

2 SYSTEM

CLOCK

CYCLES

weakstrong

very

weak

PPP

pin latch data

GPIOn,

IOn pin

glitch rejection

input data

Fig 5. Open-drain output configuration

002aab883

pin latch data

GPIO pin

glitch rejection

input data

Fig 6. Input-only configuration

002aab884

GPIO pin

glitch rejection

input data

Product data sheet Rev. 7.1 — 20 November 2017 8 of 30

NXP Semiconductors

SC18IS600

SPI to I

C-bus interface

6.2.1.4 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the pin latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a pin output.

The push-pull pin configuration is shown in Figure 7

A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit.

6.2.2 I/O pins state register (IOState)

When read, this register returns the actual state of all programmable and

quasi-bidirectional I/O pins. When written, each register bit will be transferred to the

corresponding I/O pin programmed as output.

6.2.3 I

C-bus address register (I2CAdr)

The contents of the register represents the device’s own I

C-bus address. The most

significant bit corresponds to the first bit received from the I

C-bus after a START

condition. The least significant bit is not used, but should be programmed with a ‘0’.

I2CAdr is not needed for device operation, but should be configured so that its address

does not conflict with an I

C-bus device address used by the bus master.

Fig 7. Push-pull output configuration

002aab885

strong

pin latch data

GPIO pin

glitch rejection

input data

Table 6. IOState - I/O pins state register (address 0x01) bit description

Bit Symbol Description

7:6 - reserved

5 IO5 Set the logic level on the output pins.

Write to this register:

logic 0 = set output pin to zero

logic 1 = set output pin to one

A read from this register returns states of all pins.

4IO4

3 GPIO3 (SC18IS600 only)

2GPIO2

1GPIO1

0GPIO0

Product data sheet Rev. 7.1 — 20 November 2017 9 of 30

NXP Semiconductors

SC18IS600

SPI to I

C-bus interface

6.2.4 I

C-bus clock rates register (I2CClk)

This register determines the I

C-bus clock frequency. Various clock rates are shown in

Table 7

for the SC18IS600. The frequency can be determined using Equation 1:

(1)

6.2.5 I

C-bus time-out register (I2CTO)

The time-out register is used to determine the maximum time that the I

C-bus master is

allowed to complete a transfer before setting an I

C-bus time-out interrupt.

The least significant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1

will enable the time-out function.

On the SC18IS600 the time-out oscillator operates at 57.6 kHz.

This oscillator is fed into a 16-bit down counter. The down counter’s lower nine bits are

loaded with ‘1’, while the upper seven bits are loaded with the contents of I2CTO.

The time-out value is an approximate value.

In the case of arbitration loss, the SC18IS600 will transmit a START condition when the

bus becomes free unless the time-out condition is reached. If the time-out condition is

reached, an interrupt will be generated on the INT

pin. The ‘I

C-bus time-out’ status can

be read in I2CStat.

Table 7. I

C-bus clock frequency example at 7.3728 MHz

I2CClk (decimal) I

C-bus clock frequency

5 (minimum) 369 kHz

7 263 kHz

9 204 kHz

19 97 kHz

255 (maximum) 7.2 kHz

C-bus clock frequency

7.3728 10



4 I2CClk

-------------------------------

Hz=

Table 8. I2CTO - I

C-bus time-out register (address 0x04) bit description

Bit Symbol Description

7:1 TO[7:1] Time-out value

0 TE Enable/disable time-out function

logic 0 = disable

logic 1 = enable

Fig 8. Time-out value

57.6 kHz

OSCILLATOR

002aab715

16-BIT DOWN COUNTER

[I2CTO][111111111]

time-out

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

SC18IS600IPW/S8HP

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I/O Controller Interface IC SPI to I2C-bus Interface

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