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DS8007A-EAG+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
DS8007A
Multiprotocol Dual Smart Card Interface
16 ______________________________________________________________________________________
Card Select Register (CSR)
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00110uuub on RIU = 0.
76543210
Address 00h CSR7 CSR6 CSR5 CSR4 RIU SC3 SC2 SC1
R-0 R-0 R-1 R-1 RW-0 RW-0 RW-0 RW-0
Clock Configuration Register (CCR)
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00uuuuuub on RIU = 0.
76543210
Address 01h — — SHL CST SC AC2 AC1 AC0
R-0 R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Bits 7 to 4: Identification Bits (CSR7 to CSR4). These
bits provide a method for software to identify the device
as follows:
0011 = DS8007A revision Ax
Bit 3: Reset ISO UART (RIU). When this bit is cleared
(0), most of the ISO UART registers are reset to their
initial values. This bit must be cleared for at least 10ns
prior to initiating an activation sequence. This bit must
be set (1) by software before any action on the UART
can take place.
Bits 2 to 0: Select Card Bits (SC3 to SC1). These bits
determine which IC card interface is active as shown
below. Only one bit should be active at any time, and
no card is selected after reset (i.e., SC3–SC1 = 000b).
Other combinations are invalid.
000 = No card is selected.
001 = Card A is selected.
010 = Card B is selected.
100 = AUX card interface is selected.
Bits 7 and 6: Reserved.
Bit 5: Stop High or Low (SHL). This bit determines if
the card clock stops in the low or high state when the
CST bit is active. It forces the clock to stop in a low
state when SHL = 0 or in a high state when SHL = 1.
Bit 4: Clock Stop (CST). For an asynchronous card,
this bit allows the clock to the selected card to be
stopped. When this bit is set (1), the card clock is
stopped in the state determined by the SHL bit. When
this bit is cleared (0), the card clock operation is
defined by CCR bits AC2–AC0.
Bit 3: Synchronous Clock (SC). For a synchronous
card, the card clock is controlled by software manipu-
lation of this SC, and the contact CLKx is the copy of
the value in this bit. In synchronous transmit mode, a
write to the UTR results in the least significant bit (LSb)
of the data written to the UTR being driven out on the
I/Ox pin. In synchronous receive mode, the state of the
I/Ox pin can be read from the LSb of the URR.
Bits 2 to 0: Alternating Clock Select (AC2 to AC0).
These bits select the frequency of the clock provided to
the active card interface and to the UART for the ele-
mentary time unit (ETU) generation as shown below. All
frequency changes are synchronous so that there are
no spikes or unwanted pulse widths during transitions.
f
INT
is the frequency of the internal oscillator.
AC2–AC0
000 = f
XTAL
001 = f
XTAL
/ 2
010 = f
XTAL
/ 4
011 = f
XTAL
/ 8
1xx = f
INT
/ 2
DS8007A
Multiprotocol Dual Smart Card Interface
______________________________________________________________________________________ 17
Bits 7 to 0: Programmable ETU Divider Register Bits
7 to 0 (PD7 to PD0). These bits, in conjunction with the
defined UART input clock (based upon CKU,
AC2–AC0) and the prescaler selection (PSC bit), are
used to define the ETU for the UART when interfaced to
the associated card interface. The output of the
prescaler block is further divided according to the
PD7–PD0 bits as follows:
• ETU = Prescaler output / (PD7–PD0), when
PD7–PD0 = 02h–FFh
• ETU = Prescaler output / 1, when PD7–PD0 = 00h–01h
• Prescaler output / 256 is not supported
Programmable Divider Register (PDR)
R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0.
76543210
Address 02h PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
UART Control Register 2 (UCR2)
R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0.
76 5 432 1 0
Address 03h — DISTBE/RBF DISAUX PDWN SAN AUTOC CKU PSC
R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Bit 7: Reserved.
Bit 6: Disable TBE/RBF Interrupt (DISTBE/RBF). This
bit controls whether the TBE/RBF flag can generate an
interrupt on the INT pin. When this bit is cleared to 0,
an interrupt is signaled on the INT pin in response to
the TBE/RBF flag getting set. When DISTBE/RBF is set
to 1, interrupts are not generated in response to the
TBE/RBF flag. Disabling the TBE/RBF interrupt can
allow faster communication speed with the card, but
requires that a copy of TBE/RBF in register MSR be
polled to not lose priority interrupts that can occur in
register USR.
Bit 5: Disable Auxiliary Interrupt (DISAUX). This bit
controls whether the external INTAUX pin can generate
an interrupt on the INT output pin. When this bit is
cleared to 0, a change on the INTAUX input pin results
in assertion of the INT output pin. When DISAUX is set
to 1, a change on INTAUX does not result in assertion
of the INT output pin. The INTAUXL bit is set by a
change on the INTAUX pin independent of the DISAUX
bit state. Since the INTAUX bit is set independent of the
DISAUX bit, it is advisable to read HSR (thus clearing
INTAUX) prior to clearing DISAUX to avoid an interrupt
on the INT pin. To avoid an interrupt when selecting a
different card, the DISAUX bit should be set to 1 in all
UCR2 registers.
DS8007A
Multiprotocol Dual Smart Card Interface
18 ______________________________________________________________________________________
Bit 4: Power-Down Mode Enable (PDWN). This bit
controls entry into the power-down mode. Power-down
mode can only be entered if the SUPL bit has been
cleared. When PDWN is set to 1, the XTAL1 and XTAL2
crystal oscillator is stopped, and basic functions such
as the sequencers are supported by the internal ring
oscillator. The UART is put in a suspended state, and
the clocks to the UART, the ETU unit, and the timeout
counter are gated off. During the power-down mode, it
is not possible to select a card other than the one cur-
rently selected (advisory to the programmer, selecting
another card during power-down mode is not recom-
mended). There are five ways of exiting the power-
down mode:
• Insertion of card A or card B (detected by PRLA or
PRLB).
• Withdrawal of card A or card B (detected by PRLA
or PRLB).
• Reassertion of the CS pin to select the DS8007A
(CS must be deasserted after setting PDWN = 1 for
this event to exit from power-down).
• INTAUXL bit is set due to change in INTAUX
(INTAUXL bit must be cleared first).
• Clearing of PDWN bit by software (if CS pin is
always tied to 0).
Except in the case of a read operation of register HSR,
the INT pin remains asserted in the active-low state.
The host device can read the status registers after the
oscillator warmup time, and the INT signal returns to
the high state.
Bit 3: Synchronous/Asynchronous Card Select
(SAN). This bit selects whether a synchronous or asyn-
chronous card interface is enabled. When this bit is
cleared to 0, an asynchronous card interface is expect-
ed. When this bit is set to 1, a synchronous interface is
expected. In synchronous mode, the UART is
bypassed; the SC bit controls the CLK, and I/O is trans-
acted in the LSb of UTR/URR. Card interface AUX can-
not operate in the true synchronous mode since it does
not have a CLK signal to accompany I/OAUX. However,
the SAN bit invokes the same control of I/OAUX through
UTR/URR as is given for card interfaces A and B.
Bit 2: Auto Convention Disable (AUTOC). This active-
low bit controls whether the decoding convention
should automatically be detected during the first
received character in answer-to-reset (ATR). If AUTOC
= 0, the character decoding convention is automatically
detected (while SS = 1) and the UCR1.CONV bit is writ-
ten accordingly by hardware. If AUTOC = 1, the
UCR1.CONV bit must be set by software to assign the
character decoding convention. The AUTOC bit must
not be changed during a card session.
Bit 1: Clock UART Doubler Enable (CKU). This bit
enables the effective ETU defined for the UART to last
half the number of clock cycles defined by the
AC2–AC0 and PD7–PD0 configuration (except in the
case when AC2–AC0 = 000b, where f
CLK
= f
XTAL
).
When CKU is cleared to 0, the AC2–AC0 defined f
CLK
is used for ETU timing generation. When CKU is set to
1, a clock frequency of 2 x f
CLK
is used for ETU gener-
ation.
Bit 0: Prescaler Select (PSC). When PSC = 0, the
prescaler value is 31. When PSC = 1, the prescaler
value is 32.
Guard Time Register (GTR)
R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0.
76543210
Address 05h GTR.7 GTR.6 GTR.5 GTR.4 GTR.3 GTR.2 GTR.1 GTR.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Bits 7 to 0: Guard Time Register Bits 7 to 0 (GTR.7
to GTR.0). These bits are used for storing the number
of guard time units (ETU) requested during ATR. When
transmitting, the DS8007A UART delays these numbers
of extra guard time ETU before transmitting a character
written to UTR.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

DS8007A-EAG+T

Mfr. #:
Buy DS8007A-EAG+T
Manufacturer:
Maxim Integrated
Description:
Interface - Specialized Multiprotocol Dual Smart Card Interface
Lifecycle:
New from this manufacturer.
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