DS8007A-EAG+T Datasheet DS8007A-EAG+, DS8007A-EAG+T | P28-P30

DS8007A

Multiprotocol Dual Smart Card Interface

28 ______________________________________________________________________________________

START BIT

RSTIN BIT

RSTx

CCx

CLKx

I/0x

C4x, C8x

ACTIVATION SEQUENCE

1. PCRx.START BIT IS SET BY SOFTWARE.

CONDITIONS NEEDED (IN HARDWARE) ARE:

MSR.PRx = 1 (CARD x PRESENT)

HSR.PRTLx, SUPL, PRLx, PTL = 0

2. STEP-UP CONVERTER ACTIVATED (MAY ALREADY BE ON IF ANOTHER CARD WAS ACTIVE).

3. V

CCx

ENABLED TO 1.8V, 3V, OR 5V AS SELECTED BY PCRx.1V8 AND PCR.3V/5V BITS.

CCx

RISES FROM 0V TO 1.8V, 3V, OR 5V WITH A CONTROLLED RISE TIME OF 0.17V/μs TYPICAL.

4. I/Ox IS PULLED HIGH. C4x, C8x ARE ALSO PULLED HIGH IF PCRx.C4 = 1, PCRx.C8 = 1

(RESPECTIVELY). THESE PINS HAVE INTEGRATED PULLUPS (14kΩ FOR I/Ox AND

10kΩ FOR C4x AND C8x) TO V

CCx

5. CLKx OUTPUT IS ENABLED AND RST OUTPUT IS ENABLED.

(PCRx.RSTIN SHOULD BE "0" FOR ACTIVE-LOW RSTx.)

6. PCRx.RSTIN WRITTEN TO "1" BY SOFTWARE AFTER USING TOC TO TIME SUFFICIENT

DURATION OF RSTx PIN ASSERTION.

DEACTIVATION SEQUENCE

1. PCRx.START BIT IS CLEARED BY SOFTWARE.

2. THE ACTIVE-LOW RSTx SIGNAL IS ASSERTED BY SOFTWARE.

3. THE CLKx SIGNAL IS STOPPED.

4. I/Ox, C4x, AND C8x FALL TO 0V.

5. V

CCx

IS DISABLED AND FALLS TO 0V WITH A TYPICAL RATE OF 0.17V/μs.

6. STEP-UP CONVERTER IS DEACTIVATED IF NOT IN USE BY ANOTHER CARD AND

PINS CLKx, RSTx, I/Ox, AND V

CCx

BECOME LOW IMPEDANCE TO GROUND.

TIMING

ACCORDING TO PCRx.C4, PCRx.C8 BITS

CCx

NEEDS TO DECREASE TO LESS THAN 0.4V

ACTIVATION NEEDS TO OCCUR IN UNDER 130μs

ACTIVATION SEQUENCE DEACTIVATION SEQUENCE

ACT

1234 5 123 45 66

t0 t1 t2 t3 t4 t5 t10 t11 t12 t13 t14 t15

UNDEFINED TS T0

Figure 9. Card Activation, Deactivation Sequences

Activation Sequencing

An activation sequence can only be requested by a

host device through the parallel bus interface. The host

can request an activation sequence for a specific card

(card A or card B) by setting the START bit of the PCRx

select SCx bits of the CSR). The host software can acti-

vate both cards at the same time, but only one card

can be selected to transmit/receive at a given time. The

activation sequence can only occur given satisfactory

operating conditions (e.g., the card is present and the

supply voltage is correct). These conditions can be

ascertained through the HSR, MSR, and CSR bits.

If the microcontroller attempts to write the PCRx.START

bit to 1 without having satisfied the necessary condi-

tions, the card is not activated and the bit does not

change. The activation time (from the assertion of the

START bit until the clock output is enabled) is less than

130µs. The activation sequence is detailed in Figure 9.

DS8007A

Multiprotocol Dual Smart Card Interface

______________________________________________________________________________________ 29

Deactivation Sequencing

The host device can request a deactivation sequence

by resetting the START bit to 0 for the desired card

interface. The deactivation (from the deassertion of the

START bit, step 1 of the deactivation sequence, to

CCx

decrease to less than 0.4V) is less than 150µs.

Emergency Deactivation

An emergency deactivation occurs if unsatisfactory

operating conditions are detected. An emergency deac-

tivation occurs for all activated cards in response to a

supply-voltage brownout condition (as reported by the

HSR.SUPL bit) or chip overheating (as reported by

HSR.PTL). Emergency deactivation of an individual card

can occur if a short-circuit condition is detected on the

associated V

CCx

or RSTx pin (as reported by

HSR.PRTLx) or in the case of a card takeoff (as reported

by HSR.PRLx). When an emergency deactivation occurs,

hardware automatically forces the associated START

bit(s) to the 0 state. The response of the device to the

emergency deactivation varies according to the source.

If the RSTx pin is shorted or the device overheats, the

sequencer executes a fast emergency deactivation

sequence, which ramps down V

CCx

immediately.

If the V

CCx

pin was shorted, the sequencer executes a

deactivation sequence in same way as if the START bit

was cleared to 0.

Interrupt Generation

The INT output pin signals the host device that an event

occurred that may require attention. The assertion of

the INT pin is a function of the following sources:

• A fault has been detected on card interfaces

(A or B).

•V

has dropped below the acceptable level.

• A reset is caused by externally driving the DELAY

pin to less than 1.25V.

• Excessive heating is detected (i.e., PTL = 1).

• A level change has been detected on pin PRESx or

INTAUX for the card interfaces (A, B, or AUX).

• The parity and/or frame error is detected.

• The early answer (EA) bit is set during ATR.

• The timeout counter(s) reach their terminal

count(s).

• The FIFO full status is reached.

• The FIFO overrun occurs.

• The transmit buffer is empty.

HSR.PRTLA

HSR.PRTLB

HSR.PRLA

HSR.PRLB

HSR.PTL

HSR.SUPL

USR.TO3

USR.TO1

USR.TO2

USR.EA

USR.OVR

USR.FER

USR.PE

HSR.INTAUXL

INTERRUPT

GENERATION

INT OUTPUT PIN

SCA, SCB, SCAUX

UCR2A.DISAUX

UCR2B.DISAUX

UCR2AUX.DISAUX

UCR2A.DISTBE/RBF

USR.TBE/RBF

UCR2B.DISTBE/RBF

UCR2AUX.DISTBE/RBF

SCA, SCB, SCAUX

Figure 10. Interrupt Sources

DS8007A

Multiprotocol Dual Smart Card Interface

30 ______________________________________________________________________________________

Timeout Counter Operation

The timeout counter assists the host device in timing

real-time events associated with the communication pro-

tocols: the Work Wait Time (WWT), Block Waiting Time

(BWT), etc. The timeout counter registers count ETUs, so

the input clock to the timeout counter is derived from the

output of the programmable divided clock (per card PDR

ered and have an active clock.

The timeout counter can operate as a single 24-bit

counter (TOR3–TOR1) or as separate 16-bit

(TOR3–TOR2) and 8-bit (TOR1) counters. The timeout

counters can be operated in either software mode or

start bit mode. The software mode is supported for the

16-bit and 24-bit counters. The start-bit mode is sup-

ported for all counter widths (8 bit, 16 bit, and 24 bit).

See Table 3.

Software Mode

In software mode, software configures the counter to a

starting value (while stopped) and starts the down

counter by writing the configuration value to the TOC

counter stops, the timeout flag is set, and an interrupt is

generated. If the software counter does not reach the

terminal count, it must be stopped before loading a

new value into the associated TORx counter registers.

It is possible to stop and start the 16-bit software

counter while leaving the 8-bit counter enabled (e.g.,

TOC = 65h ↔ 05h, TOC = E5h ↔ 85h, etc.).

If a compatible software mode command is written to the

TOC register before the terminal count is reached (e.g.,

write 61h to TOC register while the 65h TOC command is

running or vice versa), the new command is ignored (still

software mode), but the TOC register is updated with the

new command, and the counter continues to count until

the terminal count is reached, the respective timeout

flag(s) is set, and an interrupt is generated.

Start-Bit Mode

When configured to start-bit mode, counting starts (and

restarts for the 16-bit and 24-bit counters) when a

START bit is detected on the active card interface I/Ox

pin. When the terminal count is reached, the 8-bit

autoreload counter begins counting from the previously

programmed start value, while a 16-bit counter or 24-bit

counter stops when terminal count is reached. If the

terminal count is reached, the timeout flag is set and an

interrupt is generated. The 8-bit autoreload TOR1 regis-

ter cannot be modified during a count. The 16-bit and

24-bit counter registers can be modified during a count

without affecting the current count. The new register

data is used on the next START bit detection.

Table 3. Timeout Counter Configurations

TOC VALUE TOR3 TOR2 TOR1 DESCRIPTION

00h Stopped

All counters are stopped.

05h Stopped

Start

Bit/Autoreload

Counters 3 and 2 are stopped. Counter 1 continues in start-

bit/autoreload mode for both transmission and reception.

61h Software Stopped

Counter 1 is stopped. Counters 3 and 2 form a 16-bit counter

operating in software mode. The counter is stopped by writing 00h

to the TOC register, and must be stopped before reloading new

values in TOR3 and TOR2 registers.

65h Software

Start

Bit/Autoreload

Counters 3 and 2 form a 16-bit counter operating in software mode.

Writing 05h to the TOC register before reloading new values in

TOR2/TOR3 stops the counters. Counter 1 is operated in start-

bit/autoreload mode. The TOR1 register may not change during the

count. The 16-bit counters are stopped by setting TOC = 05h. Both

counters are stopped by setting TOC = 00h.

68h Software

Counters 1, 2, and 3 form a 24-bit counter operating in software

mode. The counter starts after the command is written to the TOC

cannot be changed without stopping the counter first.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P41

DS8007A-EAG+T

Mfr. #:

Buy DS8007A-EAG+T

Manufacturer:

Maxim Integrated

Description:

Interface - Specialized Multiprotocol Dual Smart Card Interface

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DS8007A-EAG+T

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