Rev. 1.1 4/13 Copyright © 2013 by Silicon Laboratories Si550
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)
10 MH
Z TO 1.4 GHZ
Features
Applications
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si550 supports any
frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike
traditional VCXOs, where a different crystal is required for each output
frequency, the Si550 uses one fixed crystal to provide a wide range of output
frequencies. This IC-based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low-jitter clocks in noisy environments typically found in
communication systems. The Si550 IC-based VCXO is factory-configurable
for a wide variety of user specifications, including frequency, supply voltage,
output format, tuning slope, and temperature stability. Specific configurations
are factory programmed at time of shipment, thereby eliminating the long
lead times associated with custom oscillators.
Functional Block Diagram
Available with any frequency from
10 to 945 MHz and select
frequencies to 1.4 GHz
3rd generation DSPLL
®
with
superior jitter performance (0.5 ps)
3x better temperature stability than
SAW-based oscillators
Excellent PSRR performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Fixed
Frequency
XO
Any-Frequency
10 MHz–1.4 GHz
DSPLL
®
Clock Synthesis
ADC
V
DD
Vc
OE GND
CLK–
CLK+
Ordering Information:
See page 10.
Pin Assignments:
See page 9.
(Top View)
Si5602
1
2
3
6
5
4
V
C
GND
OE
V
DD
CLK+
CLK–
Si550
REVISION D
Si550
2 Rev. 1.1
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Units
Supply Voltage
1
V
DD
3.3 V option 2.97 3.3 3.63 V
2.5 V option 2.25 2.5 2.75
V
1.8 V option 1.71 1.8 1.89
V
Supply Current I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
120
108
99
90
130
117
108
98
mA
tristate mode 60 75 mA
Output Enable (OE)
2
V
IH
0.75 x V
DD
——V
V
IL
——0.5V
Operating Temperature Range T
A
–40 85 °C
Notes:
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 10 for further details.
2. OE pin includes a 17 k resistor to V
DD
.
Table 2. V
C
Control Voltage Input
Parameter Symbol Test Condition Min Typ Max Units
Control Voltage Tuning Slope
1,2,3
K
V
10 to 90% of V
DD
33
45
90
135
180
356
ppm/V
Control Voltage Linearity
4
L
VC
BSL –5 ±1 +5 %
Incremental –10 ±5 +10
%
Modulation Bandwidth BW 9.3 10.0 10.7 kHz
V
C
Input Impedance Z
VC
500 k
Nominal Control Voltage V
CNOM
@ f
O
—V
DD
/2 V
Control Voltage Tuning Range V
C
0V
DD
V
Notes:
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 10.
2. For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3. K
V
variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope
determined with V
C
ranging from 10 to 90% of V
DD
.
Si550
Rev. 1.1 3
Table 3. CLK± Output Frequency Characteristics
Parameter Symbol Test Condition Min Typ Max Units
Nominal Frequency
1,2,3
f
O
LVDS/CML/LVPECL 10 945 MHz
CMOS 10 160 MHz
Temperature Stability
1,4
T
A
= –40 to +85 ºC –20
–50
–100
+20
+50
+100
ppm
Absolute Pull Range
1,4
APR ±12 ±375 ppm
Aging Frequency drift over first year. ±3
ppm
Frequency drift over 15 year life. ±10
Power up Time
5
t
OSC
——10ms
Notes:
1. See Section 3. "Ordering Information" on page 10 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by V
CNOM
=V
DD
/2.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to f
O
.
Table 4. CLK± Output Levels and Symmetry
Parameter Symbol Test Condition Min Typ Max Units
LVPECL Output Option
1
V
O
mid-level V
DD
– 1.42 V
DD
– 1.25 V
V
OD
swing (diff) 1.1
1.9 V
PP
V
SE
swing (single-ended) 0.55
0.95 V
PP
LVDS Output Option
2
V
O
mid-level
1.125 1.20 1.275 V
V
OD
swing (diff)
0.5 0.7 0.9 V
PP
CML Output Option
2
V
O
2.5/3.3 V option mid-level V
DD
– 1.30 V
1.8 V option mid-level V
DD
– 0.36 V
V
OD
2.5/3.3 V option swing (diff) 1.10 1.50 1.90 V
PP
1.8 V option swing (diff) 0.35 0.425 0.50 V
PP
CMOS Output Option
3
V
OH
I
OH
=32mA
0.8 x V
DD
V
DD
V
V
OL
I
OL
=32mA 0.4 V
Rise/Fall time (20/80%)
t
R,
t
F
LVPECL/LVDS/CML 350 ps
CMOS with C
L
=15pF 1 ns
Symmetry (duty cycle) SYM LVPECL: V
DD
– 1.3 V (diff)
LVDS: 1.25 V (diff)
CMOS: V
DD
/2
45 55 %
Notes:
1. 50 to V
DD
– 2.0 V.
2. R
term
= 100 (differential).
3. C
L
= 15 pF

550GF27M0000DGR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
VCXO Oscillators Differential/single-ended single frequency VCXO; 10-1417 MHz
Lifecycle:
New from this manufacturer.
Delivery:
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