Si550
Rev. 1.1 7
Table 7. CLK± Output Phase Noise (Typical)
Offset Frequency 74.25 MHz
90 ppm/V
LVPECL
155.52 MHz
45 ppm/V
LVPECL
491.52 MHz
45 ppm/V
LVPECL
622.08 MHz
135 ppm/V
LVPECL
Units
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
–87
–114
–132
–142
–148
–150
n/a
–86
–111
–128
–133
–144
–147
n/a
–75
–100
–116
–124
–135
–146
–147
–65
–90
–109
–121
–134
–146
–147
dBc/Hz
Table 8. Environmental Compliance
The Si550 meets the following qualification test requirements.
Parameter Conditions/Test Method
Mechanical Shock MIL-STD-883, Method 2002
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 203
Gross & Fine Leak MIL-STD-883, Method 1014
Resistance to Solder Heat MIL-STD-883, Method 2036
Moisture Sensitivity Level J-STD-020, MSL 1
Contact Pads J-STD-020, MSL 1
Table 9. Thermal Characteristics
(Typical values TA = 25 ºC, V
DD
=3.3V)
Parameter Symbol Test Condition Min Typ Max Unit
Thermal Resistance Junction to Ambient
JA
Still Air 84.6 °C/W
Thermal Resistance Junction to Case
JC
Still Air 38.8 °C/W
Ambient Temperature T
A
–40 85 °C
Junction Temperature T
J
——125°C
Si550
8 Rev. 1.1
Table 10. Absolute Maximum Ratings
1
Parameter Symbol Rating Units
Maximum Operating Temperature T
AMAX
85 ºC
Supply Voltage, 1.8 V Option V
DD
–0.5 to +1.9 V
Supply Voltage, 2.5/3.3 V Option V
DD
–0.5 to +3.8 V
Input Voltage V
I
–0.5 to V
DD
+ 0.3 V
Storage Temperature T
S
–55 to +125 ºC
ESD Sensitivity (HBM, per JESD22-A114) ESD 2500 V
Soldering Temperature (Pb-free profile)
2
T
PEAK
260 ºC
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
t
P
20–40 seconds
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from
www.silabs.com/VCXO for further information, including soldering profiles.
Si550
Rev. 1.1 9
2. Pin Descriptions
Table 11. Si550 Pin Descriptions
Pin Name Type Function
1 V
C
Analog Input Control Voltage
2 OE* Input
Output Enable (Polarity = High):
0 = clock output disabled (outputs tri-stated)
1 = clock output enabled
Output Enable (Polarity = Low):
0 = clock output enabled
1 = clock output disabled (outputs tri-stated)
3 GND Ground Electrical and Case Ground
4 CLK+ Output Oscillator Output
5
CLK–
(N/A for CMOS)
Output Complementary Output
(N/C for CMOS, make no external connection)
6 V
DD
Power Power Supply Voltage
*Note: OE includes 17 k pullup resistor to V
DD
. See Section 3. "Ordering Information" on page 10 for details on OE polarity
ordering options.
1
2
3
6
5
4
V
C
GND
OE
V
DD
CLK+
CLK–

550GF27M0000DGR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
VCXO Oscillators Differential/single-ended single frequency VCXO; 10-1417 MHz
Lifecycle:
New from this manufacturer.
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