M30260F8AGP#U3A Datasheet M30260F6AGP#U5A, M30260F6BGP#U9A, M30260F6AGP#U9A | P19-P21

2. CPU

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2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The register bank is comprised of seven registers (R0, R1, R2, R3,

A0, A1 and FB) out of 13 registers. There are two sets of register bank.

Figure 2.1. CPU Register

2.1 Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit

data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address regis-

ter relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as

A0.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

Data registers (Note)

Address registers (Note)

Frame base registers (Note)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

Note: These registers comprise a register bank. There are two register banks.

R0H(R0's high bits)

b15

b8 b7 b0

INTBH

USP

ISP

R0L(R0's low bits)

R1H(R1's high bits)

R1L(R1's low bits)

b31

b19

INTBL

b15

b19

b15

FLG

b15

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

The upper 4 bits of INTB are INTBH and

the lower 16 bits of INTB are INTBL.

2. CPU

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2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to 0.

2.8.3 Zero Flag (Z Flag)

This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.

2.8.4 Sign Flag (S Flag)

This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.

2.8.5 Register Bank Select Flag (B Flag)

2.8.6 Overflow Flag (O Flag)

This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1.

The I flag is cleared to 0 when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is 0; USP is selected when the U flag is 1.

The U flag is cleared to 0 when a hardware interrupt request is accepted or an INT instruction for software

interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level

0 to level 7.

If a requested interrupt has priority greater than IPL, the interrupt is enabled.

2.8.10 Reserved Area

When write to this bit, write 0. When read, its content is undefined.

3. Memory

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3. Memory

Figure 3.1 is a memory map of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T). The M16C/26A

Group provides 1-Mbyte address space addresses 0000016 to FFFFF16.

The internal ROM is allocated lower address, beginning with address FFFFF16. For example, a 64-Kbyte

internal ROM area is allocated in addresses F000016 to FFFFF16. The flash memory version has two sets

of 2-Kbyte internal ROM area, block A and block B, for data space. These blocks are allocated addresses

F00016 to FFFF16.

The fixed interrupt vectors are allocated addresses FFFDC16 to FFFFF16 and they store the start address

of each interrupt routine.

The internal RAM is allocated higher addresses, beginning with address 0040016. For example, a 1-Kbyte

internal RAM area is allocated in addresses 0040016 to 007FF16. The internal RAM is used for temporarily

storing data. The area is also used as stacks when subroutines are called or interrupt requests are ac-

knowledged.

The SFR is allocated addresses 0000016 to 003FF16. The peripheral function control registers are allo-

cated here. All blank spaces within SFR location are reserved and cannot be accessed by users.

The special page vectors are allocated addresses FFE0016 to FFFDB16. They are used for the JMPS

instruction and JSRS instruction. Refer to the Renesas publication M16C/60 and M16C/20 Series Soft-

ware Manual for details.

Figure 3.1 Memory Map

0000016

XXXXX16

Internal ROM

(Data space)

Internal ROM

(Program space)

SFR

Internal RAM

Reserved

FFE0016

FFFDC16

FFFFF16

NOTE:

1. Block A (2 Kbytes) and block B (2 Kbytes).

2. Do not write to the internal ROM in Mask ROM version.

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer

Reset

Special page

vector table

DBC

NMI

1K bytes 007FF16

00BFF16

Address XXXXX16

2K bytes

Size

Address YYYYY

16Size

F4000

FA00016

48K bytes

24K bytes

Reserved

0040016

0F00016

0FFFF16

YYYYY16

FFFFF16

(1)

F0000

64K bytes

Internal RAM

Internal ROM

(2)

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