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MT18HTF12872PDZ-667G1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to
absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol Parameter Min Max Units
V
DD
/V
DDQ
V
DD
/V
DDQ
supply voltage relative to V
SS
–0.5 2.3 V
V
IN
, V
OUT
Voltage on any pin relative to V
SS
–0.5 2.3 V
I
I
Input leakage current; Any input 0V ≤ V
IN
≤
V
DD
; V
REF
input 0V ≤ V
IN
≤ 0.95V; (All other
pins not under test = 0V)
Command/Address RAS#,
CAS#, WE# S#, CKE, ODT, BA
–5 5 µA
CK, CK# –250 250
I
OZ
Output leakage current; 0V ≤ V
OUT
≤ V
DDQ
;
DQs and ODT are disabled
DQ, DQS, DQS# –10 10 µA
I
VREF
V
REF
leakage current; V
REF
= Valid V
REF
level –36 36 µA
T
C
1
DDR2 SDRAM device operating case temper-
ature
2
Commercial 0 85 °C
Industrial –40 95
T
A
Module ambient operating temperature Commercial 0 70 °C
Industrial –40 85
Notes:
1.
The refresh rate is required to double when T
C
exceeds 85°C < T
C
≤ 95°C.
2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
able on Micron’s Web site.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. D 11/10 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades cor-
relate with component speed grades.
Table 9: Module and Component Speed Grades
DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-1GA -187E
-80E -25E
-800 -25
-667 -3
-53E -37E
-40E -5E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
DRAM Operating Conditions
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. D 11/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
I
DD
Specifications
Table 10: DDR2 I
DD
Specifications and Conditions – 1GB, Die Revision G
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD0
1
648 603 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL =
CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as I
DD4W
I
DD1
1
738 693 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
I
DD2P
2
126 126 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
I
DD2Q
2
432 396 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is HIGH, S#
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
I
DD2N
2
504 450 mA
Active power-down current: All device banks open;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
2
324 270 mA
Slow PDN exit
MR[12] = 1
162 162
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX
(I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
I
DD3N
2
594 540 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
I
DD4W
2
1188 1098 mA
Operating burst read current: All device banks open; Continuous burst read,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP
=
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
I
DD4R
2
1143 1053 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
I
DD5
2
918 873 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
I
DD6
2
126 126 mA
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
I
DD
Specifications
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. D 11/10 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MT18HTF12872PDZ-667G1

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Buy MT18HTF12872PDZ-667G1
Manufacturer:
Micron
Description:
MODULE DDR2 SDRAM 1GB 240RDIMM
Lifecycle:
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