Table 11: DDR2 I
DD
Specifications and Conditions – 2GB, Die Revision H (Continued)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating burst read current: All device banks open; Continuous burst read,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP
=
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
I
DD4R
2
1143 1053 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
I
DD5
2
1368 1323 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
I
DD6
2
126 126 mA
Operating bank interleave read current: All device banks interleaving reads,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
I
DD7
1
1953 1728 mA
Notes:
1. Value calculated as one module rank in this operating condition. All other module ranks
in I
DD2P
(CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 12: DDR2 I
DD
Specifications and Conditions – 4GB, Die Revision C
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD0
1
TBD TBD mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL =
CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as I
DD4W
I
DD1
1
TBD TBD mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
I
DD2P
2
TBD TBD mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
I
DD2Q
2
TBD TBD mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is HIGH, S#
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
I
DD2N
2
TBD TBD mA
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
I
DD
Specifications
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. D 11/10 EN
14
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© 2009 Micron Technology, Inc. All rights reserved.
