P89LPC921FDH,518 Datasheet P89LPC920FN,112, P89LPC9221FN,112, P89LPC922FDH,529 | P13-P15

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Philips Semiconductors

P89LPC920/921/922/9221

8-bit microcontrollers with two-clock 80C51 core

9397 750 14469

Product data Rev. 08 — 15 December 2004 13 of 46

[1] All ports are in input only (high impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reﬂects the cause of the P89LPC920/921/922/9221 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on

reset value is xx110000.

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after watchdog reset and is ‘0’ after power-on reset. Other resets will

not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

TRIM Internal oscillator trim register 96H - ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

[5] [6]

WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK

[4] [6]

WDL Watchdog load C1H FF 11111111

WFEED1 Watchdog feed 1 C2H

WFEED2 Watchdog feed 2 C3H

Table 4: Special function registers

…continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr.

Bit functions and addresses Reset value

MSB LSB Hex Binary

Philips Semiconductors

P89LPC920/921/922/9221

8-bit microcontrollers with two-clock 80C51 core

Product data Rev. 08 — 15 December 2004 14 of 46

9397 750 14469

8. Functional description

Remark: Please refer to the

P89LPC920/921/922/9221 User’s Manual

for a more

detailed functional description.

8.1 Enhanced CPU

The P89LPC920/921/922/9221 uses an enhanced 80C51 CPU which runs at 6 times

the speed of standard 80C51 devices. A machine cycle consists of two CPU clock

cycles, and most instructions execute in one or two machine cycles.

8.2 Clocks

8.2.1 Clock deﬁnitions

The P89LPC920/921/922/9221 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four

clock sources (see Figure 5) and can also be optionally divided to a slower frequency

(see Section 8.7 “CPU Clock (CCLK) modiﬁcation: DIVM register”).

Note: f

osc

is deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two

or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is CCLK/2

8.2.2 CPU clock (OSCCLK)

The P89LPC920/921/922/9221 provides several user-selectable oscillator options in

generating the CPU clock. This allows optimization for a range of needs from high

precision to lowest possible cost. These options are conﬁgured when the FLASH is

programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an

oscillator using an external crystal, or an external clock source. The crystal oscillator

can be optimized for low, medium, or high frequency crystals covering a range from

20 kHz to 12 MHz.

8.2.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this conﬁguration.

8.2.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic

resonators are also supported in this conﬁguration.

8.2.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic

resonators are also supported in this conﬁguration. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until V

has

reached its speciﬁed level. When system power is removed V

will fall below

Philips Semiconductors

P89LPC920/921/922/9221

8-bit microcontrollers with two-clock 80C51 core

Product data Rev. 08 — 15 December 2004 15 of 46

9397 750 14469

the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when V

falls below the minimum

speciﬁed operating voltage.

8.2.6 Clock output

The P89LPC920/921/922/9221 supports a user-selectable clock output function on

the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition

occurs if another clock source has been selected (on-chip RC oscillator, watchdog

oscillator, external clock input on X1) and if the Real-Time clock is not using the

crystal oscillator as its clock source. This allows external devices to synchronize to

the P89LPC920/921/922/9221. This output is enabled by the ENCLK bit in the TRIM

⁄

that of the CCLK. If the clock output

is not needed in Idle mode, it may be turned off prior to entering Idle, saving

additional power.

8.3 On-chip RC oscillator option

The P89LPC920/921/922/9221 has a 6-bit TRIM register that can be used to tune the

frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory

pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1% at room

temperature. End-user applications can write to the Trim register to adjust the on-chip

RC oscillator to other frequencies.

8.4 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This

oscillator can be used to save power when a high clock frequency is not needed.

8.5 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving

the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin

may be used as a standard port pin or a clock output. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until V

has

reached its speciﬁed level. When system power is removed V

will fall below

the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when V

falls below the minimum

speciﬁed operating voltage.

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P89LPC921FDH,518

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Microcontrollers - MCU 8-bit Microcontrollers - MCU 8B MCU 80C51 2/4/8KB 3V FL 256B RAM

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