LTC4355HMS#TRPBF Datasheet LTC4355IS#PBF, LTC4355IMS#PBF, LTC4355CMS#PBF | P7-P9

LTC4355

4355ff

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operation

High availability systems often employ parallel-connected

power supplies or battery feeds to achieve redundancy

and enhance system reliability. ORing diodes have been

a popular means of connecting these supplies at the

point of load. The disadvantage of this approach is the

forward voltage drop and resulting efﬁciency loss. This

drop reduces the available supply voltage and dissipates

signiﬁcant power. Using N-channel MOSFETs to replace

Schottky diodes reduces the power dissipation and

eliminates the need for costly heat sinks or large thermal

layouts in high power applications.

The LTC4355 is a positive voltage diode-OR controller

that drives two external N-channel MOSFETs as pass

transistors to replace ORing diodes. The IN and OUT

pins form the anodes and cathodes of the ideal diodes.

The source pins of the external MOSFETs are connected

to the IN pins. The drains of the MOSFETs are connected

together at the OUT pin, which is the positive supply of

the device. The gates of the external MOSFETs are driven

by the LTC4355 to regulate the voltage drop across the

pass transistors.

At power-up, the initial load current ﬂows through the

body diode of the MOSFET with the higher INx voltage.

The associated GATEx pin immediately ramps up and

turns on the MOSFET. The ampliﬁer tries to regulate the

voltage drop across the source and drain connections to

25mV. If the load current causes more than 25mV of drop,

the MOSFET gate is driven fully on and the voltage drop

is equal to R

DS(ON)

• I

LOAD

When the power supply voltages are nearly equal, this

regulation technique ensures that the load current is

smoothly shared between the MOSFETs without oscil

lation. The current ﬂowing through each pass trans-

istor depends on the R

DS(ON)

of each MOSFET and the

output impedances of the supplies.

In the event of a supply failure, such as if the supply that

is conducting most or all of the current is shorted to GND,

reverse current ﬂows temporarily through the MOSFET that

is on. This current is sourced from any load capacitance

and from the second supply through the body diode of

the other MOSFET. The LTC4355 quickly responds to this

condition, turning off the MOSFET in about 500ns. This

fast turn-off prevents the reverse current from ramping

up to a damaging level.

In the case where the forward voltage drop exceeds the

conﬁgurable fault threshold, DV

SD(FLT)

, the VDS FLT pin

pulls low. Using this pin to shunt current away from an

LED or opto-coupler provides an indication that a pass

transistor has either failed or has excessive forward current.

Additionally, in this condition the PWR FLT1 or PWRFLT2

pin pulls low to identify the faulting channel.

The PWRFLT pins also indicate if an input supply is within

regulation. When V

MON1

< 1.23V or V

MON2

< 1.23V, the

corresponding PWR FLT pin pulls low to indicate that the

input supply is low, turning off an optional LED or opto-

coupler.

The FUSEFLT pins indicate the status of input fuses. If

the voltage at one of the IN pins is less than 3.5V, the

corresponding FUSEFLT pin pulls low. The IN pins sink

a minimum of 0.5mA to guarantee that the IN pin will

pull low when the input fuse is blown open. Note that the

FUSEFLT pin will activate if the input supply is less than

3.5V even if the fuse is intact.

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applications inForMation

MOSFET Selection

The LTC4355 drives N-channel MOSFETs to conduct the

load current. The important features of the MOSFETs are

on-resistance R

DS(ON)

, the maximum drain-source voltage

DSS

, and the threshold voltage.

The gate drive for the MOSFET is guaranteed to be greater

than 4.5V when the supply voltage at V

OUT

is between

9V and 20V. When the supply voltage at V

OUT

is greater

than 20V, the gate drive is guaranteed to be greater than

10V. The gate drive is limited to less than 18V. This allows

the use of logic level threshold N-channel MOSFETs and

standard N-channel MOSFETs above 20V. An external

Zener diode can be used to clamp the potential from the

MOSFET’s gate to source if the rated breakdown voltage

is less than 18V. See the Typical Applications section for

an example.

The maximum allowable drain-source voltage, BV

DSS

must be higher than the supply voltages. If an input is

connected to GND, the full supply voltage will appear

across the MOSFET.

If the voltage drop across either MOSFET exceeds the

configurable DV

SD(FLT)

fault threshold, the VD SFLT

pin and the PWRFLT pin corresponding to the fault-

ing channel pull low. The R

DS(ON)

should be small

enough to conduct the maximum load current while

not triggering a fault, and to stay within the MOS

FET’s power rating at the maximum load current

• R

DS(ON)

Fault Conditions

The LTC4355 monitors fault conditions and shunts current

away from LEDs or opto-couplers, turning each one off to

indicate a speciﬁc fault condition (see Table 1).

When the voltage drop across the pass transistor is

higher than the conﬁgurable DV

SD(FLT)

fault threshold, the

internal pull-down at the VDS FLT pin and the PWRFLT1 or

PWRFLT2 pin corresponding to the faulting channel turns

on. The DV

SD(FLT)

threshold is conﬁgured by the SET pin.

Tying SET to GND, tying SET to a 100k resistor connected

to GND, or ﬂoating SET conﬁgures DV

SD(FLT)

to 250mV,

500mV, or 1.5V respectively.

Table 1. Fault Table

SD1

< DV

SD(FLT)

IN1

> 3.5V

MON1

> 1.23V

VDSFLT*

FUSEFLT1

PWRFLT1

True True T

rue Hi-Z Hi-Z Hi-Z

True True False Hi-Z Hi-Z Pull-Down

True False True Hi-Z Pull-Down Hi-Z

True False False Hi-Z Pull-Down Pull-Down

False True True Pull-Down Hi-Z Pull-Down

False True False Pull-Down Hi-Z Pull-Down

False False True Pull-Down Pull-Down Pull-Down

False False False Pull-Down Pull-Down Pull-Down

*DV

SD2

< DV

SD(FLT)

Fault conditions that may cause a high voltage across the

pass transistor include: a MOSFET open on the higher

supply, excessive MOSFET current due to overcurrent

on the load or a shorted MOSFET on the lower supply.

During startup or when a switchover between supplies

occurs, the VD SFLT pin and PWR FLT1 or PWRFLT2 pin

may momentarily indicate that the forward voltage has

exceeded the programmed threshold during the short

interval when the MOSFET gate ramps up and the body

diode conducts.

The PWR FLT pins are additionally used to indicate if either

input supply is below its normal regulation range. If the

voltage at the MON1 or MON2 pin is less than V

MON(TH)

typically 1.23V, the corresponding PWR FLT1 or PWR FLT2

pin will pull low. A resistive divider connected to the input

supply drives the MON pin for the corresponding supply,

conﬁguring the PWRFLT threshold for that supply. Be sure

to account for the tolerance of the MON pin threshold,

the resistor tolerances, and the regulation range of the

supply being monitored. Also, ensure that the voltage on

the MON pin will not exceed 7V.

The FUSEFLT pins are used to indicate the status of the

input fuses. If one of the IN pins falls below V

INx(TH)

, typi-

cally 3.5V, the FUSEFLT pin cor

responding to that supply

will pull low. The IN pins each sink a minimum of 0.5mA,

enough to pull the pin low after an input fuse blows open.

If there is a possibility that the MOSFET leakage current

can be greater than 0.5mA, a resistor can be connected

between the IN pin and GND to sink more current. Note

that if the input supply voltage is less than V

INx(TH)

the

FUSEFLT pin will pull low.

LTC4355

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applications inForMation

System Power Supply Failure

The LTC4355 automatically supplies load current from the

system input supply with the higher voltage. If this supply

shorts to ground, reverse current begins to ﬂow through

the pass transistor temporarily and the transistor begins

to turn off. When this reverse current creates –25mV of

voltage drop across the drain and source pins of the pass

transistor, a fast pull-down circuit engages to drive the

gate low faster.

The remaining system power supply delivers the load cur

rent through the body diode of its pass transistor until the

channe

l turns on. The LTC4355 ramps the gate up with

20µA, turning on the N-channel MOSFET to reduce the

voltage drop across it.

Input Short-Circuit Faults

The dynamic behavior of an active, ideal diode entering

reverse bias is most accurately characterized by a delay

followed by a period of reverse recovery. During the delay

phase some reverse current is built up, limited by para-

sitic resistances and inductances. During the reverse re-

covery phase, energy stored in the parasitic inductances

is trans

ferred to other elements in the circuit. Current

slew rates during reverse recovery may reach 100A/µs

or higher.

High slew rates coupled with parasitic inductances in se

ries with the input and output paths may cause potentially

destr

uctive transients to appear at the IN and OUT pins of

the LTC4355 during reverse recovery. A zero impedance

short-circuit directly across an input that is supplying

current is especially troublesome because it permits the

highest possible reverse current to build up during the

delay phase. When the MOSFET ﬁnally commutates the

reverse current the LTC4355 IN pin experiences a nega

tive voltage spike, while the OUT pin spikes in the positive

irecti

on.

To prevent damage to the LTC4355 under conditions of

input short-circuit, protect the IN pins and OUT pin as

shown in Figure 1. The IN pins are protected by clamping

to the GND pin in the negative direction. Protect the OUT

pin with a clamp, such as with a TVS or TransZorb, or with

a local bypass capacitor of at least 10µF. In low voltage

applications the MOSFET’s drain-source breakdown may

be sufﬁcient to protect the OUT pin, provided BV

DSS

< 100V.

Parasitic inductance between the load bypass or the

second supply and the LTC4355 allows a zero impedance

input short to collapse the voltage at the OUT pin, which

increases the total turn-off time (t

OFF

). For applications

up to 30V, bypass the OUT pin with 39µF; above 30V use

at least 100µF. One capacitor serves to guard against OUT

collapse and also protect OUT from voltage spikes.

Figure 1. Reverse Recovery Produces Inductive Spikes at the IN and OUT Pins.

The Polarity of Step Recovery Spikes Is Shown Across Parasitic Inductances

LTC4355

GND

GATE1 GATE2IN1 OUTIN2

FDS3672

REVERSE

RECOVERY

CURRENT

FDS3672

IN1

OUT

IN2

SBR1U150SA

INPUT PARASITIC

INDUCTANCE

+ –

OUTPUT PARASITIC

INDUCTANCE

+ –

INPUT PARASITIC

INDUCTANCE

– +

OUT

10µF

LOAD

CLAMP

SMAT70A

REVERSE RECOVERY CURRENT

4355 F01

IN1

SBR1U150SA

INPUT

SHORT

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LTC4355HMS#TRPBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Power Management Specialized - PMIC Pos Hi V Ideal Diode-OR w/ In S & Fuse M

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LTC4355HMS#TRPBF

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