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8344BYILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
8344I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 201510
APPLICATION INFORMATION
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R2/
R1 = 0.609.
INPUTS:
CLK/nCLK INPUTS
For applications not requiring the use of the differential input, both
CLK and nCLK can be left fl oating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUTS
All unused LVCMOS output can be left fl oating. There should be
no trace attached.
8344I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 201511
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
PP and
V
CMR input requirements. Figures 2A to 2E show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples only.
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
Please consult with the vendor of the driver component to confi rm
the driver termination requirements. For example in Figure 2A, the
input termination applies for IDT HiPerClockS LVHSTL drivers. If
you are using an LVHSTL driver from another vendor, use their
termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8344I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 201512
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 8344I is: 1,449
TABLE 6. θ
JA
VS. AIR FLOW TABLE FOR 48 LEAD LQFP
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

8344BYILFT

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Clock Drivers & Distribution 24 LVCMOS OUT BUFFER
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