8344I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 20157
TABLE 5B. AC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Maximum Output Frequency 100 MHz
tp
LH
Propagation Delay,
Low to High; NOTE 1
f 100MHz
2.6 4.5 ns
tp
HL
Propagation Delay,
High to Low; NOTE 1
f 100MHz
2.6 4.5 ns
tsk(b) Bank Skew; NOTE 2, 6 150 ps
tsk(o) Output Skew; NOTE 3, 6 275 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 600 ps
t
R
Output Rise Time; NOTE 5 30% to 70% 300 1700 ps
t
F
Output Fall Time; NOTE 5 30% to 70% 300 1400 ps
odc Output Duty Cycle 40% 60% %
t
EN
Output Enable Time; NOTE 5 f = 66.7MHz 6 ns
t
DIS
Output Disable TIme; NOTE 5 f = 66.7MHz 6 ns
All parameters measured at 100MHz unless noted otherwise.
NOTE 1: Measured from the diffferential input crossing point to V
DDO
/2.
NOTE 2: Defi ned as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltage and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defi ned in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, V
DD
= V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Maximum Output Frequency 100 MHz
tp
LH
Propagation Delay,
Low to High; NOTE 1
f 100MHz 2.7 4.3 ns
tp
HL
Propagation Delay,
High to Low; NOTE 1
f 100MHz 2.7 4.3 ns
tsk(b) Bank Skew; NOTE 2, 6 150 ps
tsk(o) Output Skew; NOTE 3, 6 275 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 600 ps
t
R
Output Rise Time; NOTE 5 30% to 70% 300 1700 ps
t
F
Output Fall Time; NOTE 5 30% to 70% 300 1400 ps
odc Output Duty Cycle 40% 60% %
t
EN
Output Enable Time; NOTE 5 f = 66.7MHz 6 ns
t
DIS
Output Disable TIme; NOTE 5 f = 66.7MHz 6 ns
For NOTES, please see Table 5B above.
8344I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 20158
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
GND
CLK0,
CLK1
nCLK0,
nCLK1
V
DD
PART-TO-PART SKEW OUTPUT SKEW
2.5V OUTPUT LOAD AC TEST CIRCUIT
8344I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 20159
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

8344BYILFT

Mfr. #:
Manufacturer:
Description:
Clock Drivers & Distribution 24 LVCMOS OUT BUFFER
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New from this manufacturer.
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