OC-48/OC-48 FEC Clock and
Data Recovery
Data Sheet
ADN2811
Rev. C Document Feedback
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FEATURES
Meets SONET requirements for jitter transfer/generation/
tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
1.9 GHz minimum bandwidth
Patented clock recovery architecture
Loss of signal detect range: 3 mV to 15 mV
Single reference clock frequency for both native SONET and
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK
LVPECL/LVDS/LVCMOS/LVTTL compatible inputs
(LVPECL/LVDS only at 155.52 MHz)
19.44 MHz on-chip oscillator to be used with external crystal
Loss of lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm, 48-lead LFCSP
APPLICATIONS
SONET OC-48, SDH STM-16, and 15/14 FEC
WDM transponders
Regenerators/repeaters
Test equipment
Backplane applications
PRODUCT DESCRIPTION
The ADN2811 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at OC-48 and
OC-48 FEC rates. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.
The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both the 2.48 Gbps and 2.66 Gbps
digital wrapper rates are supported by the ADN2811, without
any change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
The ADN2811 is available in a compact, 7 mm × 7 mm, 48-lead
chip scale package.
FUNCTIONAL BLOCK DIAGRAM
LEVEL
DETECT
DA TA
RETIMING
FRACTIONAL
DIVIDER
FREQUENCY
LOCK
DETECTOR
LOOP
FILTER
PHASE
SHIFTER
PHASE
DET.
VCO
XTAL
OSC
LOOP
FILTER
QUANTIZER
/n
ADN2811
SLICEP/N VCC VEE
CF1 CF2
LOL
REFSEL[0..1]
REFCLKP/N
XO1
XO2
REFSEL
RATECLKOUTP/NDATAOUTP/NSDOUT
THRADJ
VREF
NIN
PIN
2
2
22
2
03019-B-001
Figure 1.
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Last Content Update: 08/30/2016
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ADN2811 Data Sheet
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Product Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution .................................................................................. 5
Pin Configuration and Functional Descriptions .......................... 6
Definition of Terms .......................................................................... 8
Maximum, Minimum, and Typical Specifications................... 8
Input Sensitivity and Input Overdrive ....................................... 8
Single-Ended vs. Differential ...................................................... 8
LOS Response Time ..................................................................... 9
Jitter Specifications ....................................................................... 9
Theory of Operation ...................................................................... 10
Functional Description .................................................................. 12
Clock and Data Recovery .......................................................... 12
Limiting Amplifier ..................................................................... 12
Slice Adjust .................................................................................. 12
Loss of Signal (LOS) Detector .................................................. 12
Reference Clock .......................................................................... 12
Lock Detector Operation .......................................................... 13
Squelch Mode ............................................................................. 14
Test Modes: Bypass and Loopback ........................................... 14
Applications Information .............................................................. 15
PCB Design Guidelines ............................................................. 15
Choosing AC-Coupling Capacitors ......................................... 17
DC-Coupled Application .......................................................... 18
LOL Toggling during Loss of Input Data ................................ 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/16Rev. B to Rev. C
Changes to Figure 2 and Table 3 ..................................................... 6
Changes to Figure 19 ...................................................................... 16
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
5/04Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Table 6 and Table 7 ..................................................... 13
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
12/02Rev. 0 to Rev. A.
Change to Functional Description Reference Clock ................. 10
Updated Outline Dimensions ....................................................... 16

ADN2811ACPZ-CML-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC CLK DATA REC SDH 2.66GHZ
Lifecycle:
New from this manufacturer.
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