ADN2811ACPZ-CML-RL Datasheet ADN2811ACPZ-CML-RL | P13-P15

ADN2811 Data Sheet

Rev. C | Page 12 of 20

FUNCTIONAL DESCRIPTION

CLOCK AND DATA RECOVERY

The ADN2811 recovers clock and data from serial bit streams at

OC-48 as well as the 15/14 FEC rates. The data rate is selected

by the RATE input (see Table 4).

Table 4. Data Rate Selection

RATE

Data Rate

Frequency (MHz)

0 OC-48 2488.32

1 OC-48 FEC 2666.06

LIMITING AMPLIFIER

The limiting amplifier has differential inputs (PIN/NIN) that

are internally terminated with 50 Ω to an on-chip voltage ref-

erence (VREF = 0.6 V typically). These inputs are normally

ac-coupled, although dc coupling is possible as long as the input

common-mode voltage remains above 0.4 V (see Figure 22,

Figure 23, and Figure 24). Input offset is factory trimmed to

achieve better than 4 mV typical sensitivity with minimal drift.

The limiting amplifier can be driven differentially or single-

ended.

SLICE ADJUST

The quantizer slicing level can be offset by ±100 mV to mitigate

the effect of amplified spontaneous emission (ASE) noise by

applying a differential voltage input of ±0.8 V to SLICEP/N

inputs. If no adjustment of the slice level is needed, SLICEP/N

must be tied to VCC.

LOSS OF SIGNAL (LOS) DETECTOR

The receiver front end level signal detect circuit indicates when

the input signal level has fallen below a user adjustable threshold.

The threshold is set with a single external resistor from Pin 1,

THRADJ, to GND. The LOS comparator trip point versus the

resistor value is illustrated in Figure 4 (this is only valid for

SLICEP = SLICEN = VCC). If the input level to the ADN2811

drops below the programmed LOS threshold, SDOUT (Pin 45)

indicates the loss of signal condition with a Logic 1. The LOS

response time is ~300 ns by design, but is dominated by the RC

time constant in ac-coupled applications.

If using the LOS detector, the quantizer slice adjust pins must

both be tied to VCC. This is to avoid interaction with the LOS

threshold level.

Note that it is not expected to use both LOS and slice adjust at

the same time; systems with optical amplifiers need the slice

adjust to evade ASE. However, a loss of signal in an optical link

that uses optical amplifiers causes the optical amplifier output

to be full-scale noise. Under this condition, the LOS does not

detect the failure. In this case, the loss of lock signal indicates

the failure because the CDR circuitry is unable to lock onto a

signal that is full-scale noise.

REFERENCE CLOCK

There are three options for providing the reference frequency to

the ADN2811: differential clock, single-ended clock, or crystal

oscillator. See Figure 14, Figure 15, and Figure 16 for example

configurations.

100k

Ω 100k

Ω

UFFER

ADN2811

VCC/2

REFCLK

CRYSTAL

OSCILLATO

XO1

XO2

VCC

REFSEL

03019-B-014

Figure 14. Differential REFCLK Configuration

OUT

100kΩ 100kΩ

BUFFER

ADN2811

VCC/2

REFCLKN

REFCLKP

CRYSTAL

OSCILLATOR

XO2

VCC

REFSEL

CLK

OSC

VCC

03019-B-015

Figure 15. Single-Ended REFCLK Configuration

100kΩ 100kΩ

BUFFER

ADN2811

VCC/2

REFCLKN

REFCLK

CRYSTAL

OSCILLATOR

XO1

XO2

REFSEL

19.44MHz

VCC

003019-B-016

Figure 16. Crystal Oscillator Configuration

Data Sheet ADN2811

Rev. C | Page 13 of 20

The ADN2811 can accept any of the following reference clock

frequencies: 19.44 MHz, 38.88 MHz, 77.76 MHz at LVTTL/

LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/

LVDS levels via the REFCLKN/P inputs, independent of data

rate. The input buffer accepts any differential signal with a peak-to-

peak differential amplitude of greater than 100 mV (for example,

LVPECL or LVDS) or a standard single-ended low voltage TTL

input, providing maximum system flexibility. The appropriate

division ratio can be selected using the REFSEL0/1 pins, according

to Table 5. Phase noise and duty cycle of the reference clock are

not critical, and 100 ppm accuracy is sufficient.

Table 5. Reference Frequency Selection

REFSEL

REFSEL[1..0]

Applied Reference Frequency (MHz)

1 00 19.44

38.88

1 10 77.76

1 11 155.52

0 XX REFCLKP/N Inactive. Use 19.44 MHz

XTAL oscillator on Pins XO1, XO2 (Pull

REFCLKP to VCC).

An on-chip oscillator to be used with an external crystal is also

provided as an alternative to using the REFCLKN/P inputs.

Details of the recommended crystal are given in Table 6.

Table 6. Required Crystal Specifications

Parameter Value

Mode Series Resonant

Frequency/Overall Stability 19.44 MHz ±100 ppm

Frequency Accuracy ±100 ppm

Temperature Stability ±100 ppm

Aging ±100 ppm

ESR 50 Ω max

REFSEL must be tied to VCC when the REFCLKN/P inputs are

active, or tied to VEE when the oscillator is used. No connection

between the XO pin and REFCLK input is necessary (see Figure 14,

Figure 15, and Figure 16). Note that the crystal must operate in

series resonant mode, which renders it insensitive to external

parasitics. No trimming capacitors are required.

LOCK DETECTOR OPERATION

The lock detector monitors the frequency difference between

the VCO and the reference clock and deasserts the loss of lock

signal when the VCO is within 500 ppm of center frequency

(see Figure 17). This enables the phase loop, which pulls the

VCO frequency in the remaining amount and also acquires

phase lock. Once locked, if the input frequency error exceeds

1000 ppm (0.1%), the loss of lock signal is reasserted and control

returns to the frequency loop, which reacquires and maintains

a stable clock signal at the output.

The frequency loop requires a single external capacitor between

CF1 and CF2. The capacitor specification is given in Table 7.

Table 7. Recommended C

Capacitor Specification

Parameter Value

Temperature Range −40°C to +85°C

Capacitance >3.0 µF

Leakage <80 nA

Rating >6.3 V

1000 500 0 500

1000 f

VCO

ERROR

(

ppm)

LOL

03019-B-017

Figure 17. Transfer Function of LOL

ADN2811 Data Sheet

Rev. C | Page 14 of 20

50Ω

Ω

UANTIZER

ADN2811

VREF

NIN

50Ω 50Ω

VCC

TDINP/N

LOOPEN BY

ASS

CDR

RETIMED

A CL

1 0

DATAOUTP/N CLKOUTP/N SQUELCH

FROM

ANTIZER

OUTPU

03019-B-018

Figure 18. Test Modes

SQUELCH MODE

When the squelch input is driven to a TTL high state, both the

clock and data outputs are set to the zero state to suppress

downstream processing. If desired, this pin can be directly

driven by the LOS detector output, SDOUT. If the squelch

function is not required, the pin must be tied to VEE.

TEST MODES: BYPASS AND LOOPBACK

When the bypass input is driven to a TTL high state, the

quantizer output is connected directly to the buffers driving the

data out pins, thus bypassing the clock recovery circuit (see

Figure 18). This feature can help the system deal with

nonstandard bit rates.

The loopback mode can be invoked by driving the LOOPEN pin

to a TTL high state, which facilitates system diagnostic testing.

This connects the test inputs (TDINP/N) to the clock and data

recovery circuit (per Figure 18). The test inputs have internal

50 Ω terminations and can be left floating when not in use.

TDINP/N are CML inputs and can only be dc-coupled when

being driven by CML outputs. The TDINP/N inputs must be

ac-coupled if being driven by anything other than CML outputs.

Bypass and loopback modes are mutually exclusive. Only one of

these modes can be used at any given time. The ADN2811 is put

into an indeterminate state if the BYPASS and LOOPEN pins are

set to Logic 1 at the same time.

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ADN2811ACPZ-CML-RL

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IC CLK DATA REC SDH 2.66GHZ

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