ADN2811 Data Sheet
Rev. C | Page 6 of 20
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Type
1
Description
1
THRADJ
AI
LOS Threshold Setting Resistor.
2, 26, 28
VCC
P
Analog Supply.
3, 9, 16, 19, 22, 27,
29, 33, 34, 42, 43, 46
VEE P Ground.
4
VREF
AO
Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
5
PIN
AI
Differential Data Input. CML.
6
NIN
AI
Differential Data Input. CML.
7
SLICEP
AI
Differential Slice Level Adjust Input.
8
SLICEN
AI
Differential Slice Level Adjust Input.
10
LOL
DO
Loss of Lock Indicator. LVTTL active high.
11 XO1 AO Crystal Oscillator.
12
XO2
AO
Crystal Oscillator.
13
REFCLKN
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
14
REFCLKP
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
15
REFSEL
DI
Reference Source Select. 0 = on-chip oscillator with external crystal; 1 = external clock source, LVTTL.
17 TDINP AI Differential Test Data Input.
18
TDINN
AI
Differential Test Data Input.
20, 47
VCC
P
Digital Supply.
21
CF1
AO
Frequency Loop Capacitor.
23
REFSEL1
DI
Reference Frequency Select (See Table 5) LVTTL.
24
REFSEL0
DI
Reference Frequency Select (See Table 5) LVTTL.
25
CF2
AO
Frequency Loop Capacitor.
30
RATE
DI
Data Rate Select (See Table 4) LVTTL.
31, 32
NC
DI
No Connect.
35, 36
VCC
P
Output Driver Supply.
37
DATAOUTN
DO
Differential Retimed Data Output. CML.
38
DATAOUTP
DO
Differential Retimed Data Output. CML.
39
SQUELCH
DI
Disable Clock and Data Outputs. Active high. LVTTL.
40 CLKOUTN DO Differential Recovered Clock Output. CML.
41
CLKOUTP
DO
Differential Recovered Clock Output. CML.
44
BYPASS
DI
Bypass CDR Mode. Active high. LVTTL.
45
SDOUT
DO
Loss of Signal Detect Output. Active high. LVTTL.
48
LOOPEN
DI
Enable Test Data Inputs. Active high. LVTTL.
Not applicable EPAD FP
Exposed Pad. Exposed pad is tied off to VCC plane with vias.
1
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output, FP = floating pad.
Data Sheet ADN2811
Rev. C | Page 7 of 20
T
S
T
H
CLKOUT
P
DATAOUTP/N
03019-B-003
Figure 3. Output Timing
RESISTANCE (k)
0 100
18
16
0
mV
8
6
4
2
12
10
14
THRADJ RESISTOR VS. LOSTRIP POINT
10 20 30 40 50 60 70 80 90
03019-B-004
Figure 4. LOS Comparator Trip Point Programming
OUTP
OUTN
V
SE
V
CML
0V
OUTP–OUTN
V
SE
V
DIFF
03019-B-005
Figure 5. Single-Ended vs. Differential Output Specs
ADN2811 Data Sheet
Rev. C | Page 8 of 20
DEFINITION OF TERMS
MAXIMUM, MINIMUM, AND TYPICAL
SPECIFICATIONS
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribution.
This procedure is intended to tolerate production variations. If
the mean shifts by 1.5 standard deviations, the remaining 4.5
standard deviations still provide a failure rate of only 3.4 parts per
million. For all tested parameters, the test limits are guardbanded
to account for tester variation and therefore guarantee that no
device is shipped outside of data sheet specifications.
INPUT SENSITIVITY AND INPUT OVERDRIVE
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the logic
output of the quantizer and the analog voltage input is shown in
Figure 6. For a sufficiently large positive input voltage, the output is
always Logic 1; similarly for negative inputs, the output is always
Logic 0. However, the transitions between output Logic Levels 1
and 0 are not at precisely defined input voltage levels but occur
over a range of input voltages. Within this zone of confusion,
the output may be either 1 or 0, or it may even fail to attain a
valid logic state. The width of this zone is determined by the
input voltage noise of the quantizer. The center of the zone of
confusion is the quantizer input offset voltage. Input overdrive
is the magnitude of signal required to guarantee the correct
logic level with 1 × 10
−10
confidence level.
0
1
INPUT (V p-p)
OUTPUT
NOISE
SENSITIVITY
(2× OVERDRIVE)
OFFSET
OVERDRIVE
03019-B-006
Figure 6. Input Sensitivity and Input Overdrive
SINGLE-ENDED VS. DIFFERENTIAL
AC-coupling typically drives the inputs to the quantizer. The
inputs are internally dc biased to a common-mode potential of
~0.6 V. Driving the ADN2811 single-ended and observing the
quantizer input with an oscilloscope probe at the point indicated in
Figure 7 shows a binary signal with an average value equal to the
common-mode potential and instantaneous values both above
and below the average value. It is convenient to measure the peak-
to-peak amplitude of this signal and call the minimum required
value the quantizer sensitivity. Referring to Figure 6, since both
positive and negative offsets need to be accommodated, the
sensitivity is twice the overdrive.
50 50
QUANTIZER
+
ADN2811
VREF
PIN
SCOPE
PROBE
VREF
10mV p-p
03019-B-007
Figure 7. Single-Ended Sensitivity Measurement
50 50
Q
UANTIZER
+
ADN2811
VREF
NIN
PIN
SCOP
E
PROBE
VREF
5mV p-p
03019-B-008
Figure 8. Differential Sensitivity Measurement
Driving the ADN2811 differentially (see Figure 8), sensitivity
seems to improve by observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2811 quantizer. However, the single-ended probe measures
only half the signal. The true quantizer input signal is twice this
value since the other quantizer input is complementary to the
signal being observed.

ADN2811ACPZ-CML-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC CLK DATA REC SDH 2.66GHZ
Lifecycle:
New from this manufacturer.
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