LTC3722-1/LTC3722-2
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occur, independent of load current as long as energy in
the transformers magnetizing and leakage inductance is
greater than the capacitive energy. That is, 1/2 (LM + LI)
IM2 > 1/2 • 2 COSS V
IN
2 — the worst case occurs
when the load current is zero. This condition is usually
easy to meet. The magnetizing current is virtually constant
during this transition because the magnetizing inductance
has positive voltage applied across it throughout the low
to high transition. Since the leg is actively driven by this
current source, it is called the active or linear transition.
When the voltage on the active leg has risen to V
IN
,
MOSFET MC is switched on by the ZVS circuitry. The
primary current now flows through the two high side
MOSFETs (MA and MC). The transformers secondary
windings are electrically shorted at this time since both
ME and MF are “ON”. As long as positive current flows
in LO1 and LO2, the transformer primary (magnetizing)
inductance is also shorted through normal transformer
action. MA and MF turn off at the end of State 2.
State 3 (Passive Transition)
MA turns off when the oscillator timing period ends, i.e.,
the clock pulse toggles the internal flip-flop. At the instant
MA turns off, the voltage on the MA/MB junction begins to
decay towards the lower supply (GND). The energy available
to drive this transition is limited to the primary leakage
inductance and added commutating inductance which
have (I
MAG
+ I
OUT
/2N) flowing through them initially. The
magnetizing and output inductors do not contribute any
energy because they are effectively shorted as mentioned
previously, significantly reducing the available energy. This
is the major difference between the active and passive
transitions. If the energy stored in the leakage and com-
mutating inductance is greater than the capacitive energy,
the transition will be completed successfully. During the
transition, an increasing reverse voltage is applied to the
leakage and commutating inductances, helping the overall
primary current to decay. The inductive energy is thus
resonantly transferred to the capacitive elements, hence,
the term passive or resonant transition. Assuming there
is sufficient inductive energy to propel the bridge leg to
GND, the time required will be approximately equal to:
π
2
LC
When the voltage on the passive leg nears GND, MOSFET
MB is commanded “ON” by the ZVS circuitry. Current
continues to increase in the leakage and external series
inductance which is opposite in polarity to the reflected
output inductor current. When this current is equal in
magnitude to the reflected output current, the primary
current reverses direction, the opposite secondary winding
becomes forward biased and a new power pulse is initi-
ated. The time required for the current reversal reduces
the effective maximum duty cycle and must be considered
when computing the power transformer turns ratio. If
ZVS is required over the entire range of loads, a small
commutating inductor is added in series with the primary
to aid with the passive leg transition, since the leakage
inductance alone is usually not sufficient and predictable
enough to guarantee ZVS over the full load range.
State 4 (Power Pulse 2)
During power pulse 2, current builds up in the primary
winding in the opposite direction as power pulse 1. The
primary current consists of reflected output inductor cur-
rent and current due to the primary magnetizing inductance.
At the end of State 4, MOSFET MC turns off and an active
transition, essentially similar to State 2 but opposite in
direction (high to low), takes place.
Zero Voltage Switching (ZVS)
A lossless switching transition requires that the respective
full bridge MOSFETs be switched to the “ON” state at the
exact instant their drain-to-source voltage is zero. Delaying
the turn-on results in lower efficiency due to circulating cur-
rent flowing in the body diode of the primary side MOSFET
rather than its low resistance channel. Premature turn-on
produces hard switching of the MOSFETs, increasing noise
and power dissipation.
LTC3722-1/LTC3722-2 Adaptive Delay Circuitry
The LTC3722-1/LTC3722-2 monitors both the input supply
and instantaneous bridge leg voltages, and commands
a switching transition when the expected zero voltage
condition is reached. DirectSense technology provides
optimal turn-on delay timing, regardless of input voltage,
output load, or component tolerances. The DirectSense
technique requires only a simple voltage divider sense
OPERATION
LTC3722-1/LTC3722-2
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network to implement. If there is not enough energy to
fully commutate the bridge leg to a ZVS condition, the
LTC3722-1/LTC3722-2 automatically overrides the Di-
rectSense circuitry and forces a transition. The override
or default delay time is programmed with a resistor from
DPRG to V
REF
.
Adaptive Mode
The LTC3722-1/LTC3722-2 are configured for adaptive
delay sensing with three pins, ADLY, PDLY and SBUS.
ADLY and PDLY sense the active and passive delay legs
respectively via a voltage divider network, as shown in
Figure 2.
delays exist between the time at which the LTC3722-1/
LTC3722-2 controller output transitions, to the time at
which the power MOSFET switches on due to MOSFET
turn-on delay and external driver circuit delay. Ideally, we
want the power MOSFET to switch at the instant there
is zero volts across it. By setting a threshold voltage for
ADLY and PDLY corresponding to several volts across the
MOSFET, the LTC3722-1/LTC3722-2 can anticipate a zero
voltage VDS and signal the external driver and switch to
turn-on. The amount of anticipation can be tailored for
any application by modifying the upper divider resistor(s).
The LTC3722-1/LTC3722-2 DirectSense circuitry sources
a trimmed current out of PDLY and ADLY (proportional
to SBUS) after a low to high level transition occurs. This
provides hysteresis and noise immunity for the PDLY and
ADLY circuitry, and sets the high to low threshold on ADLY or
PDLY to nearly the same level as the low to high threshold,
thereby making the upper and lower MOSFET VDS switch
points virtually identical, independent of V
IN
.
Example: V
IN
= 48V nominal (36V to 72V)
1. Set up SBUS: 1.5V is desired on SBUS with V
IN
= 48V.
Set divider current to 100µA.
R1=
1.5V
100µA
= 15k
R2 =
48V 1.5V
100µA
= 465k
An optional small capacitor (0.001µF) can be added
across R1 to decouple noise from this input.
2. Set up ADLY and PDLY: 7V of anticipation is desired
in this circuit to account for the delays of the external
MOSFET driver and gate drive components.
R3, R4 = 1k, sets a nominal 1.5mA in the divider chain
at the threshold.
R5,R6 =
(48V 7V 1.5V)
1.5mA
= 26.3k,
use (2) equal 13k segments.
OPERATION
The threshold voltage on PDLY and ADLY for both the ris-
ing and falling transitions is set by the voltage on SBUS.
A buffered version of this voltage is used as the threshold
level for the internal DirectSense circuitry. At nominal V
IN
,
the voltage on SBUS is set to 1.5V by an external voltage
divider between V
IN
and GND, making this voltage directly
proportional to V
IN
. The LTC3722-1/LTC3722-2 DirectSense
circuitry uses this characteristic to zero voltage switch
all of the external power MOSFETs, independent of input
voltage.
ADLY and PDLY are connected through voltage dividers to
the active and passive bridge legs respectively. The lower
resistor in the divider is set to 1k. The upper resistor in
the divider is selected for the desired positive transition
trip threshold.
To set up the ADLY and PDLY resistors, first determine at
what drain to source voltage to turn-on the MOSFETs. Finite
SBUS
ADLY
PDLY
R2
R5
R6
R1
R3
1k
R4
1k
R
CS
A
B
C
D
V
IN
372212 F02
Figure 2. Adaptive Mode
LTC3722-1/LTC3722-2
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Fixed Delay Mode
The LTC3722-1/LTC3722-2 provides the flexibility through
the SBUS pin to disable the DirectSense delay circuitry
and enable fixed ZVS delays. The level of fixed ZVS delay
is proportional to the voltage programmed through the
voltage divider on the PDLY and ADLY pins (see Figure 3
for more detail).
Programming Adaptive Delay Time-Out
The LTC3722-1/LTC3722-2 controllers include a feature to
program the maximum time delay before a bridge switch
turn on command is summoned. This function will come
into play if there is not enough energy to commutate a
bridge leg to the opposite supply rail, therefore bypass-
ing the adaptive delay circuitry. The time delay can be
set with an external resistor connected between DPRG
and V
REF
(see Figure 4). The nominal regulated voltage
on DPRG is 2V. The external resistor programs a current
which flows into DPRG. The delay can be adjusted from
approximately 35ns to 300ns, depending on the resistor
value. If DPRG is left open, the delay time is approximately
400ns. The amount of delay can also be modulated based
on an external current source that feeds current into DPRG.
Care must be taken to limit the current fed into DPRG to
350µA or less.
Powering the LTC3722-1/LTC3722-2
The LTC3722-1/LTC3722-2 utilize an integrated V
CC
shunt
regulator to serve the dual purposes of limiting the volt-
age applied to V
CC
as well as signaling that the chip’s bias
voltage is sufficient to begin switching operation (under-
voltage lockout). With its typical 10.2V turn-on voltage
and 4.2V UVLO hysteresis, the LTC3722-1/LTC3722-2
is tolerant of loosely regulated input sources such as an
auxiliary transformer winding. The V
CC
shunt is capable
of sinking up to 25mA of externally applied current. The
UVLO turn-on and turn-off thresholds are derived from
an internally trimmed reference making them extremely
accurate. In addition, the LTC3722-1/LTC3722-2 exhibits
very low (145µA typ) start-up current that allows the use
of 1/8W to 1/4W trickle charge start-up resistors.
The trickle charge resistor should be selected as follows:
R
START(MAX)
= V
IN(MIN)
10.7V
250µA
Adding a small safety margin and choosing standard
values yields:
APPLICATION V
IN
RANGE R
START
DC/DC 36V TO 72V 100k
Off-Line 85V to 270V
RMS
430k
PFC Preregulator 390V
DC
1.4M
V
CC
should be bypassed with a 0.1µF to 1µF multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the V
CC
supply before
the bootstrap winding, or an auxiliary regulator circuit
takes over.
C
HOLDUP
= (I
CC
+ I
DRIVE
)
t
DELAY
3.8V
(minimum UVLO hysteresis)
OPERATION
Figure 3. Setup for Fixed ZVS Delays
ADLY
PDLY
V
REF
SBUS
372212 F03
R1
R2
R3
Figure 4. Delay Timeout Circuitry
+
TURN-ON
OUTPUT
SBUS
+
V
2V
V
REF
DPRG
R
DPRG
372212 F04

LTC3722EGN-2#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Sync 2x Mode PhModulated Full Bridge Cnt
Lifecycle:
New from this manufacturer.
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