ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 3
ICS9DB803D REV N 071013
Pin Descriptions for OE_INV=0
PIN # PIN NAME PIN TYPE DESCRIPTION
1SRC_DIV# IN
Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
2VDDR PWR
3.3V power for differential input clock (receiver). This VDD should be
treated as an analog power rail and filtered appropriately.
3 GND PWR Ground pin.
4 SRC_IN IN 0.7 V Differential SRC TRUE input
5 SRC_IN# IN 0.7 V Differential SRC COMPLEMENTARY input
6OE_0 IN
Active high input for enabling output 0.
0 =disable outputs, 1= enable outputs
7OE_3 IN
Active high input for enabling output 3.
0 =disable outputs, 1= enable outputs
8 DIF_0 OUT 0.7V differential true clock output
9 DIF_0# OUT 0.7V differential Complementary clock output
10 GND PWR Ground pin.
11 VDD PWR Power supply, nominal 3.3V
12 DIF_1 OUT 0.7V differential true clock output
13 DIF_1# OUT 0.7V differential Complementary clock output
14 OE_1 IN
Active high input for enabling output 1.
0 =disable outputs, 1= enable outputs
15 OE_2 IN
Active high input for enabling output 2.
0 =disable outputs, 1= enable outputs
16 DIF_2 OUT 0.7V differential true clock output
17 DIF_2# OUT 0.7V differential Complementary clock output
18 GND PWR Ground pin.
19 VDD PWR Power supply, nominal 3.3V
20 DIF_3 OUT 0.7V differential true clock output
21 DIF_3# OUT 0.7V differential Complementary clock output
22 BYPASS#/PLL IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
24 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
