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9FGL0641AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
6-OUTPUT 3.3V PCIE CLOCK GENERATOR 4 DECEMBER 1, 2016
9FGL06 DATASHEET
Test Loads
Alternate Terminations
The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
REF Output
33
REF Output Test Load
5pF
Zo = 50 ohms
Terminations
Device Zo (Ω)Rs (Ω)
9FGL0641 100 None needed
9FGL0651 100 7.5
9FGL06P1 100 Prog.
9FGL0641 85 N/A
9FGL0651 85 None needed
9FGL06P1 85 Prog.
DECEMBER 1, 2016 5 6-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL06 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGL06. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Electrical Characteristics–SMBus Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Supply Voltage VDDxx Applies to VDD, VDDA and VDDIO, if present. -0.5 3.9 V 1,2
Input Voltage V
IN
-0.5 V
DD
+ 0.5V V 1, 3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.9 V 1
Storage Temperature Ts -65 150 °C 1
Junction Temperature Tj 125 °C 1
Input ESD protection ESD prot Human Body Model 2500 V 1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 4.5V.
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V 0.8 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V 2.1 3.6 V
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
2.7 3.6 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
SMB
SMBus operating frequency 500 kHz 2
1
Guaranteed by design and characterization, not 100% tested in production.
2.
The device must be powered up for the SMBus to function.
6-OUTPUT 3.3V PCIE CLOCK GENERATOR 6 DECEMBER 1, 2016
9FGL06 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDxxx
Supply voltage for core, analog and single-ended
LVCMOS outputs.
3.135 3.3 3.465 V
IO Supply Voltage VDDIO Supply voltage for differential Low Power outputs. 0.9975 1.05-3.3 3.465 V
Ambient Operating
Temperature
T
AMB
Industrial range -40 25 85 °C
Input High Voltage V
IH
0.75 V
DDx
V
DDx
+ 0.3 V
Input Low Voltage V
IL
-0.3 0.25 V
DDx
V
Input High Voltage V
IHtri
0.75 V
DDx
V
DD
+ 0.3 V
Input Mid Voltage V
IMtri
0.4 V
DDx
0.5 V
DDx
0.6 V
DDx
V
Input Low Voltage V
ILtri
-0.3 0.25 V
DDx
V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down
resistors
-50 50 uA
Input Frequency F
in
XTAL, or X1 input 8 25 40 MHz 4
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.3 1.8 ms 1,2
SS Modulation Frequency f
MO
D
(Triangular Modulation) 30 31.6 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
123clocks1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
28 300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 1,2
Trise t
R
Rise time of single-ended control inputs 5 ns 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
4
The 9FGLxxP1 devices can be programmed for various input frequencies from 8 to 40MHz. The 9FGLxx41/51 devices use 25MHz.
3
Time from deassertion until outputs are >200 mV
Input Current
Capacitance
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9FGL0641AKILF

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Clock Generators & Support Products 6 Output 3.3V PCIe 100 Ohm w/ ZO
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