NCP1602
www.onsemi.com
17
When the load is at its maximum (the maximum V
ctrl
value and inductor peak current limitation is not triggering),
the controller runs in CrM mode and the frequency
(@V
in
=V
in,max
) has its minimum value. As we start
decreasing the output power, the V
ctrl
voltage decreases, the
switching frequency (@V
in
=V
in,max
) increases and the
controller stays in CrM mode until V
ctrl
reaches a threshold
voltage named V
ctrl,th,*
. From this point, continuing to
reduce the output power makes the controller to continue
increase the dead time (T
DT
) after the end of
demagnetization resulting in a DCM conduction mode and
a switching frequency decrease (Frequency Foldback).
When the output power is reduced and we enter DCM
mode, the switching frequency decreases down to a value
given by the following equation, which is valid down to
before entering SKIP mode. This minimum DCM frequency
value is dominated by the dead time value, t
ON
plus t
DEMAG
being negligible versus t
DT
that has reached is maximum
value t
DT,max
.
SW, DCM, min +
t
) t
) t
[
t
(eq. 1
In order to have, depending on customer application, a
different limitation of the maximum switching frequency
(@V
in
=V
in,max
), as well as different V
ctrl
thresholds for
CrM to DCM boundary, different product versions are made
available (see Table 2).
CrM−DCM and DCM−CrM Transition Hysteresis
Hesitation of the system to transition between the modes
CrM and DCM may have a consequences on inductor
current shape and distort the mains current, resulting in a bad
PF value when the operating point is at the CrM−DCM
boundary.
To avoid such undesired behavior, a 40−mV hysteresis is
added on V
ctrl
threshold. The V
ctrl
threshold for transitioning
from CrM to DCM mode is named V
ctrl,th,
* (see Table 6) and
the V
ctrl
threshold for transitioning from DCM to CrM mode
is V
ctrl,th
,* + 40 mV.
NCP1602 Skip Mode (Active on Versions [B**] and
[D**], Disabled on Versions [A**] and [C**])
The circuit also skips cycles when V
ctrl
decreases towards
V
SKIP−L
threshold. A comparator monitors the V
ctrl
voltage
and inhibits the drive when V
ctrl
is lower than the SKIP
Mode threshold V
SKIP−L
. Switching resumes when V
ctrl
exceeds V
SKIP−H
threshold. The skip mode capability is
disabled whenever the PFC stage is not in nominal operation
(as dictated by the PFCOK signal − see PFCOK Operation
section).
NCP1602 On−time Modulation and V
TON
Processing
Circuit
Let’s analyze the ac line current absorbed by the PFC
boost stage. The initial inductor current at the beginning of
each switching cycle is always zero. The coil current ramps
up when the MOSFET is on. The slope is (V
in
/L) where L is
the coil inductance. At the end of the on−time (t
1
), the
inductor starts to demagnetize. The inductor current ramps
down until it reaches zero. The duration of this phase is (t
2
).
In some cases, the system enters then the dead−time (t
3
) that
lasts until the next clock is generated.
One can show that the ac line current is given by:
I
in
+ V
in
t
1
ǒ
t
1
) t
2
Ǔ
2T L
(eq. 2)
Where
T + t
1
) t
2
) t
3
(eq. 3)
is the switching period and V
in
is the ac line rectified voltage.
In light of this equation, we immediately note that I
in
is
proportional to V
in
if [t
1.
(t
1
+t
2
)/T] is a constant.
I
peak,max
I
ind
t
1
t
2
0
T
t
3
V
in
time
L1 D1
Q1
V
in
V
out
I
ind
C
bulk
C
in
DRV
R
sense
time
Figure 33. PFC Boost Converter and Inductor Current in DCM
