85411 Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 20, 20164
TABLE 4. AC CHARACTERISTICS, V
DD
= 3.3V±10% TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 650 MHz
t
PD
Propagation Delay; NOTE 1 1.5 2.5 ns
tsk(o) Output Skew; NOTE 2, 4 20 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
(12kHz to 20MHz) 0.05 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% @ 50MHz 150 350 ps
odc Output Duty Cycle
> 500MHz 47 53 %
500MHz
48 52 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet
specifi cations after thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ 650MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
85411 Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 20, 20165
ADDITIVE PHASE JITTER
Input/Output Additive Phase Jit-
ter @ 200MHz (12kHz to 20MHz)
= 0.05ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M 500M
The spectral purity in a band at a specifi c offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specifi ed plot in many applications. Phase
noise is defi ned as the ratio of the noise power present in a 1Hz
band at a specifi ed offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
As with most timing specifi cations, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
oor of the equipment is higher than the noise fl oor of the device.
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specifi ed, the phase noise
is called a dBc value, which simply means dBm at a specifi ed offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
This is illustrated above. The device meets the noise fl oor of what
is shown, but can actually be lower. The phase noise is dependent
on the input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
85411 Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 20, 20166
PARAMETER MEASUREMENT INFORMATION
DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
PROPAGATION DELAY OUTPUT RISE/FALL TIME
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
DIFFERENTIAL OUTPUT VOLTAGE SETUP

85411AMLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Low Skew 1-to-2 Diff to LVDS Fanout Buff
Lifecycle:
New from this manufacturer.
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