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PBLS4004D,115
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
PBLS4004D_3
© NXP B.V
. 2009. All rights reserved.
Product data sheet
Rev
. 03 — 6 January 2009
9 of 15
NXP Semiconductors
PBLS4004D
40 V PNP BISS loadswitch
I
C
/I
B
=2
0
(1)
T
amb
= 100
°
C
(2)
T
amb
=2
5
°
C
(3)
T
amb
=
−
55
°
C
T
amb
=2
5
°
C
(1)
I
C
/I
B
= 100
(2)
I
C
/I
B
=5
0
(3)
I
C
/I
B
=1
0
Fig 9.
TR1 (PNP): Collector-emitter saturation
v
oltage as a function of collector current;
typical values
Fig 10.
TR1 (PNP): Collector-emitter saturation
v
oltage as a function of collector current;
typical values
I
C
/I
B
=2
0
(1)
T
amb
= 100
°
C
(2)
T
amb
=2
5
°
C
(3)
T
amb
=
−
55
°
C
T
amb
=2
5
°
C
(1)
I
C
/I
B
= 100
(2)
I
C
/I
B
=5
0
(3)
I
C
/I
B
=1
0
Fig 11.
TR1 (PNP): Collector-emitter saturation
resistance as a function of collector current;
typical values
Fig 12.
TR1 (PNP): Collector-emitter saturation
resistance as a function of collector current;
typical values
006aaa466
I
C
(mA)
−
10
−
1
−
10
4
−
10
3
−
1
−
10
2
−
10
−
10
−
1
−
1
V
CEsat
(V)
−
10
−
2
(3)
(1)
(2)
006aaa471
I
C
(mA)
−
10
−
1
−
10
4
−
10
3
−
1
−
10
2
−
10
−
10
−
2
−
10
−
1
−
1
−
10
V
CEsat
(V)
−
10
−
3
(3)
(2)
(1)
006aaa470
I
C
(mA)
−
10
−
1
−
10
4
−
10
3
−
1
−
10
2
−
10
1
10
10
2
10
3
R
CEsat
(
Ω
)
10
−
1
(3)
(1)
(2)
006aaa472
I
C
(mA)
−
10
−
1
−
10
4
−
10
3
−
1
−
10
2
−
10
1
10
10
2
10
3
R
CEsat
(
Ω
)
10
−
1
(3)
(2)
(1)
PBLS4004D_3
© NXP B.V
. 2009. All rights reserved.
Product data sheet
Rev
. 03 — 6 January 2009
10 of 15
NXP Semiconductors
PBLS4004D
40 V PNP BISS loadswitch
V
CE
=5V
(1)
T
amb
= 150
°
C
(2)
T
amb
=2
5
°
C
(3)
T
amb
=
−
40
°
C
I
C
/I
B
=2
0
(1)
T
amb
= 100
°
C
(2)
T
amb
=2
5
°
C
(3)
T
amb
=
−
40
°
C
Fig 13.
TR2 (NPN): DC current gain as a function of
collector current; typical values
Fig 14.
TR2 (NPN): Collector-emitter saturation
v
oltage as a function of collector current;
typical values
V
CE
= 0.3 V
(1)
T
amb
=
−
40
°
C
(2)
T
amb
=2
5
°
C
(3)
T
amb
= 100
°
C
V
CE
=5V
(1)
T
amb
=
−
40
°
C
(2)
T
amb
=2
5
°
C
(3)
T
amb
= 100
°
C
Fig 15.
TR2 (NPN): On-state input volta
ge as a
function of collector current; typical values
Fig 16.
TR2 (NPN): Off-state input volta
ge as a
function of collector current; typical values
I
C
(mA)
10
−
1
10
2
10
1
006aaa038
10
2
10
10
3
h
FE
1
(1)
(2)
(3)
006aaa039
I
C
(mA)
11
0
2
10
10
−
1
V
CEsat
(V)
10
−
2
(1)
(2)
(3)
006aaa040
I
C
(mA)
10
−
1
10
2
10
1
1
10
V
I(on)
(V)
10
−
1
(1)
(2)
(3)
006aaa041
I
C
(mA)
10
−
2
10
1
1
10
−
1
1
10
V
I(off)
(V)
10
−
1
(1)
(3)
(2)
PBLS4004D_3
© NXP B.V
. 2009. All rights reserved.
Product data sheet
Rev
. 03 — 6 January 2009
11 of 15
NXP Semiconductors
PBLS4004D
40 V PNP BISS loadswitch
8.
P
ac
ka
ge outline
9.
P
ac
king inf
ormation
[1]
For further information and the av
ailability of packing methods
, see
Section 13
.
[2]
T1: normal taping
[3]
T2: rev
erse taping
Fig 17.
Pac
kage outline SO
T457 (SC-74)
04-11-08
Dimensions in mm
3.0
2.5
1.7
1.3
3.1
2.7
pin 1 index
1.9
0.26
0.10
0.40
0.25
0.95
1.1
0.9
0.6
0.2
13
2
4
5
6
T
able 8.
P
acking methods
The indicated -xxx are the last three digits of the 12NC ordering code.
[1]
T
ype number
Pa
c
k
ag
e
Description
P
acking quantity
3
000
10
000
PBLS4004D
SO
T457
4 mm pitch, 8 mm tape and reel; T1
[2]
-115
-135
4 mm pitch, 8 mm tape and reel; T2
[3]
-125
-165
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
PBLS4004D,115
Mfr. #:
Buy PBLS4004D,115
Manufacturer:
Nexperia
Description:
Bipolar Transistors - Pre-Biased BISS LDSWITCH TAPE-7
Lifecycle:
New from this manufacturer.
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PBLS4004D,115