32K/16K x 8, 32K x 9
Dual-Port Static RAM
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06045 Rev. *D Revised August 11, 2005
Features
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12
[1]
/15/20 ns
• Low operating power
— Active: I
CC
= 180 mA (typical)
— Standby: I
SB3
= 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
•INT
flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
• Pb-Free packages available
Notes:
1. See page 7 for Load Conditions.
2. I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices.
3. BUSY
is an output in master mode and an input in slave mode.
4. A
0
–A
13
for 16K; A
0
–A
14
for 32K devices.
I/O
Control
Address
Decode
A
0L
–A
13/14L
CE
L
OE
L
R/W
L
BUSY
L
I/O
Control
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
Logic Block Diagram
A
0L
–A
13/14L
True Dual-Ported
RAM Array
A
0R
–A
13/14R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
Address
Decode
A
0R
–A
13/14R
[2]
[2]
[3]
[3]
R/W
L
OE
L
I/O
0L
–I/O
7/8L
CE
L
R/W
R
OE
R
I/O
0R
–I/O
7/8R
CE
R
14/15
8/9
14/15
8/9
14/15 14/15
[4]
[4]
[4]
[4]
CY7C006A
CY7C007A
CY7C017A32K/16K x 8, 32K x 9
Dual-Port Static RAM
