CY7C006A/CY7C007A
CY7C016A/CY7C017A
Document #: 38-06045 Rev. *D Page 8 of 20
Switching Characteristics Over the Operating Range
[12]
Parameter Description
CY7C006A
CY7C007A
CY7C016A
CY7C017A
Unit
–12
[1]
–15 –20
Min. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 12 15 20 ns
t
AA
Address to Data Valid 12 15 20 ns
t
OHA
Output Hold From Address Change 3 3 3 ns
t
ACE
[13]
CE LOW to Data Valid 12 15 20 ns
t
DOE
OE LOW to Data Valid 8 10 12 ns
t
LZOE
[14, 15, 16]
OE LOW to Low Z 3 3 3 ns
t
HZOE
[14, 15, 16]
OE HIGH to High Z 10 10 12 ns
t
LZCE
[14, 15, 16]
CE LOW to Low Z 3 3 3 ns
t
HZCE
[14, 15, 16]
CE HIGH to High Z 10 10 12 ns
t
PU
[16]
CE LOW to Power-Up 0 0 0 ns
t
PD
[16]
CE HIGH to Power-Down 12 15 20 ns
WRITE CYCLE
t
WC
Write Cycle Time 12 15 20 ns
t
SCE
[13]
CE LOW to Write End 10 12 15 ns
t
AW
Address Valid to Write End 10 12 15 ns
t
HA
Address Hold From Write End 0 0 0 ns
t
SA
[13]
Address Set-Up to Write Start 0 0 0 ns
t
PWE
Write Pulse Width 10 12 15 ns
t
SD
Data Set-Up to Write End 10 10 15 ns
t
HD
[19]
Data Hold From Write End 0 0 0 ns
t
HZWE
[15, 16]
R/W LOW to High Z 10 10 12 ns
t
LZWE
[15, 16]
R/W HIGH to Low Z 3 3 3 ns
t
WDD
[17]
Write Pulse to Data Delay 25 30 45 ns
t
DDD
[17]
Write Data Valid to Read Data Valid 20 25 30 ns
BUSY TIMING
[18]
t
BLA
BUSY LOW from Address Match 12 15 20 ns
t
BHA
BUSY HIGH from Address Mismatch 12 15 20 ns
t
BLC
BUSY LOW from CE LOW 12 15 20 ns
t
BHC
BUSY HIGH from CE HIGH 12 15 17 ns
t
PS
Port Set-Up for Priority 5 5 5 ns
Notes:
12.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI
/I
OH
and 30-pF load capacitance.
13.To access RAM, CE
= L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
SCE
time.
14.At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
15.Test conditions used are Load 3.
16.This parameter is guaranteed but not tested.
17.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
18.Test conditions used are Load 2.
19. For 15 ns industrial parts t
HD
Min. is 0.5 ns.
