CY7C006A/CY7C007A
CY7C016A/CY7C017A
Document #: 38-06045 Rev. *D Page 11 of 20
Write Cycle No. 1: R/W Controlled Timing
[27, 28, 29, 30]
Write Cycle No. 2: CE Controlled Timing
[27, 28, 29, 34]
Notes:
27.R/W
or CE must be HIGH during all address transitions.
28.A write occurs during the overlap (t
SCE
or t
PWE
) of a LOW CE or SEM.
29.t
HA
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
30.If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified t
PWE
.
31.To access RAM, CE
= V
IL
, SEM = V
IH
.
32.Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
33.During this period, the I/O pins are in the output state, and input signals must not be applied.
34.If the CE
or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms (continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
[32]
[32]
[30]
[31]
NOTE 33
NOTE 33
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
[31]
