AD421
–7–
REV. C
Reference Section
The AD421 contains an on-chip 1.21 V bandgap reference
which is used as part of the voltage regulator loop. A bandgap
reference is also used to generate two references voltages
which are available for use external to the AD421. Figure 5
shows the reference section of the AD421. The REF OUT1 pin
provides a buffered +1.25 V reference voltage which can supply
up to 0.5 mA of external current. The REF OUT2 pin provides
a +2.5 V reference voltage which is also capable of providing
0.5 mA of external current. To use the AD421 with its own
reference, simply connect the REF OUT2 pin to the REF IN
pin of the device. Alternatively, the part can be used with an
external reference by connecting the external reference between
REF IN and COM.
When REF OUT1 and REF OUT2 are used in application
circuits, external 4.7 µF capacitors are required on the reference
pins to provide compensation and ensure stable operation of the
references. These capacitors can be omitted if the internal refer-
ences are not required.
1.21V
112.5k⍀
134k⍀
75k⍀
121k⍀
V
CC
LV
4.7F
DRIVE
2.5V
BANDGAP
REFERENCE
AD421
50k⍀
REF OUT2
(2.5V)
50k⍀
4.7F
REF OUT1
(1.25V)
Figure 5. Reference Section
REF OUT2 is sensed internally, and if more than 0.5 mA is
drawn externally from this reference, the chip goes into a power
on reset state. In this state the sigma-delta DAC is disabled, the
internal oscillator is stopped and the input data latch is cleared.
REF OUT1 has limited current sinking capability. If REF
OUT1 is required to sink current, a resistive load of 100 kΩ
to COM should be added in addition to the 4.7 µF capacitor.
USING THE AD421
The AD421 can be programmed for normal 4 mA to 20 mA
operation or for alarm current operation. For normal operation,
the coding is 16-bit straight (natural) binary over an output
current range of 4 mA to 20 mA. For alarm current operation,
the coding is also straight binary but with 17 bits of resolution
over twice the span, 0 mA to 32 mA, although the part should
not be programmed outside the range of 3.5 mA to 24 mA. To
determine whether data written to the part is normal 4 mA to
20 mA data or alarm current data, the number of clock pulses
between two successive LATCH pulses are counted. If the num-
ber of pulses is 0–16 (modulo 32), it chooses normal mode; if it
is 17–31 (modulo 32), it chooses alarm current range.
4 mA to 20 mA Coding
Table II shows the ideal input-code-to-output-current relation-
ship for normal operation of the AD421. The output current
values shown assume a REF IN voltage of +2.5 V. With a
REF IN of +2.5 V, 1 LSB = 16 mA/65,536 = 244 nA. Figure 6
shows a timing diagram for programming the AD421 for normal
4 mA to 20 mA operation, the AD421 outputting a current
AD421
BOOST
40⍀
80k⍀
LOOP RTN
SWITCHED
CURRENT
SOURCES
Figure 4. Current Amplifier
The BOOST pin is normally tied to the V
CC
pin. As the DAC
input code varies from all zeros to full scale, the output current
from the NPN transistor and thus the total loop current varies
from 4 mA to 20 mA. With BOOST and V
CC
tied together, the
external FET (DN25D) has to supply the full range of loop
current (4 mA to 20 mA).
Digital Interface
The digital interface on the AD421 consists of just three wires:
DATA, CLOCK and LATCH. The interface connects directly
to the serial ports of commonly-used microcontrollers without
the need for any external glue logic. Data is loaded MSB first
into an input shift register on the rising edge of the CLOCK
signal and is transferred to the DAC latch on the rising edge of
the LATCH signal. The timing diagrams for the serial interface
are shown in Figure 1 and Figure 2.
The data to be loaded to the AD421’s input shift register takes
two forms; normal 4 mA to 20 mA data or alarm current data.
The first form is where the AD421 operates over its normal
4 mA to 20 mA output range with 16 bits of resolution between
these endpoints. The second form allows the user to program a
current value outside this range as an indication from the trans-
mitter than there is a problem with the transducer. The AD421
counts the number of clock pulses which it receives between
LATCH signals as a means of determining whether the data
clocked in is 4 mA to 20 mA data or alarm current data.
If there are 16 rising clock edges between successive LATCH
pulses, then the data being loaded to the input shift register is
assumed to be normal 4 mA to 20 mA data. On the rising edge
of the LATCH signal, the input shift register data is transferred
to the DAC latch in a 16-bit parallel transfer. In this case, the
16 bits of data in the DAC latch program the output current
between 4 mA for all 0s and 20 mA for all 1s (see Table II).
Data transferred to the AD421 should be MSB first.
If there are more than 16 clock pulses between successive
LATCH pulses, then the data being loaded to the input shift
register is assumed to be alarm current data. In this case, the
AD421 accepts 17 bits of data into its shift register. For situa-
tions where there are more than 17 clocks in the serial write
operation (for example, 24 clocks in a 3 × 8-bit transfer from the
serial port of a microcontroller) the AD421 simply accepts the
last 17 bits of the serial write operation. Data transferred in this
serial write operation is LSB last (i.e., the MSB is loaded on the
17th rising clock edge prior to the LATCH pulse). On the rising
edge of the LATCH signal, the input shift register data is trans-
ferred to the DAC latch in a 17-bit parallel transfer. In this
case, the 17 bits of data in the DAC latch program the output
current between 0 mA for all 0s and 32 mA for all 1s (see Table
III). However, in practice the AD421 cannot reliably produce a
current less than 3.5 mA or more than 24 mA.
