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9UMS9001AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15
9UMS9001
IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
PC MAIN CLOCK - CK540
1
Recommended Application:
Features/Benefits:
Calistoga Based Ultra-Mobile PC (UMPC)
• Supports Dothan ULV CPUs with 100 and
133 MHz CPU outputs
• Dedicated TEST/SEL and TEST/MODE pins
saves isolation resistors on pins
• PCI_SRC and CPU STOP inputs for power
manangment
• Fully integrated Vreg
• Integrated series resistors on differential
outputs
• Supports split rail operation for maximum
power savings
• Also runs from single 3.3V rail
• 1.05V-3.3V support for differential VDDIO
Pin Configuration
Output Features:
• 2 - CPU Low Power differential push-pull pairs
• 1 - ITP low power differential push-pull pair
• 4 - SRC low power differential push-pull pairs
• 1 - LCD100 SSCD low power differential
push-pull pair
• 1 - DOT96 low power differential push-pull
pair
• 3 - PCI, 33MHz
• 1 - USB, 48MHz
• 1 - REF, 14.31818MHz
GNDREF
FSLC
CK_PWRGD#/PD
VDDCPUPLL_3.3
CPU0T_LPRS
CPU0C_LPRS
GNDCPU
VDDIO_CPU
CPU1T_LPRS
CPU1C_LPRS
CPUITPT_LPRS
CPUITPC_LPRS
CPU_STOP#
FSLB
56 55 54 53 52 51 50 49 48 47 46 45 44 43
X2 1 42 CLKREQ2#
X1 2 41 CLKREQ3#
VDDREFIO_3.3 3 40 VDDCORE_3.3
REF0 4 39 SRC3T_LPRS
SDATA
538
SRC3C_LPRS
SCLK
6
37 SRC2T_LPRS
TEST_SEL 7 36 SRC2C_LPRS
TEST_MODE 8 35 VDDIO_SRC
PCI_STOP# 9 34 GNDSRC
VDDIO_PCI3.3 10 33 SRC1T_LPRS
PCI0 11 32 SRC1C_LPRS
PCI1 12 31 SRC0T_LPRS
PCI_F2 13 30 SRC0C_LPRS
GNDPCI 14 29 CLKREQ0#
15 16 17 18 19 20 21 22 23 24 25 26 27 28
GND48
USB_48MHz
VDD48IO_3.3
VDD48PLL_3.3
VDDIO_96Mhz
DOT96C_LPRS
DOT96T_LPRS
GND
GND
LCD100C_LPRS
LCD100T_LPRS
VDDIO_LCD
VDDLCDPLL_3.3
CLKREQ1#
56-pin MLF
ICS9UMS9001
IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
2
Pin Description
PIN # PIN NAME TYPE DESCRIPTION
1 X2 OUT Crystal output, nominally 14.318MHz.
2 X1 IN Crystal input, Nominally 14.318MHz.
3 VDDREFIO_3.3 PWR Power pin for the REF output and crystal oscillator. 3.3V nominal.
4 REF0 OUT 3.3V 14.318MHz reference clock
5 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
6 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
7TEST_SEL IN
3.3V input that puts the part in test mode. This is a realtime input. See the Test Clarification Table for
details.
8 TEST_MODE IN When Test mode is selected, this chooses either hi-Z or REF/N for the outputs.
9 PCI_STOP# IN 3.3V tolerant input that stops all PCI and SRC clocks, except those set to be free running.
10 VDDIO_PCI3.3 PWR 3.3V power supply for the PCI outputs
11 PCI0 OUT 3.3V PCI clock output.
12 PCI1 OUT 3.3V PCI clock output.
13 PCI_F2 OUT Free running 3.3V PCI clock output
14 GNDPCI PWR Ground for PCI output clocks.
15 GND48 PWR Ground for the USB clock.
16 USB_48MHz OUT Fixed 3.3V 48MHz USB clock output
17 VDD48IO_3.3 PWR 3.3V Power supply for the 48MHz output
18 VDD48PLL_3.3 PWR 3.3V Power supply for the 48/96MHz PLL
19 VDDIO_96Mhz PWR Power supply for DOT96 output. VDD_IO = 1.05 to 3.3V +/-5%.
20 DOT96C_LPRS OUT
Complement side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external
series resistor required).
21 DOT96T_LPRS OUT
True side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external series
resistor required).
22 GND PWR Ground for 96MHz output
23 GND PWR Ground for LCD 100 MHz output.
24 LCD100C_LPRS OUT
Complement side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated
(No external series resistor required).
25 LCD100T_LPRS OUT
True side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated (No
external series resistor required).
26 VDDIO_LCD PWR Power supply for LCD100 output. VDD_IO = 1.05 to 3.3V +/-5%.
27 VDDLCDPLL_3.3 PWR 3.3V Power supply for the LCD100 Spreading PLL
28 CLKREQ1# IN
Clock request input for SRC output pair 1. See the SRC, LCD, DOT Power Management Table for
details
IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
3
Pin Description (continued)
PIN # PIN NAME TYPE DESCRIPTION
29 CLKREQ0# IN
Clock request input for SRC output pair 0. See the SRC, LCD, DOT Power Management Table for
details
30 SRC0C_LPRS OUT
Complement side of low-power CK505-type SRC0 differential clock. Rs is integrated (No external
series resistor required).
31 SRC0T_LPRS OUT
True side of low-power CK505-type SRC0 differential clock. Rs is integrated (No external series
resistor required).
32 SRC1C_LPRS OUT
Complement side of low-power CK505-type SRC1 differential clock. Rs is integrated (No external
series resistor required).
33 SRC1T_LPRS OUT
True side of low-power CK505-type SRC1 differential clock. Rs is integrated (No external series
resistor required).
34 GNDSRC PWR Ground for SRC clocks
35 VDDIO_SRC PWR Power supply for SRC outputs. VDD_IO = 1.05 to 3.3V +/-5%.
36 SRC2C_LPRS OUT
Complement side of low-power CK505-type SRC2 differential clock. Rs is integrated (No external
series resistor required).
37 SRC2T_LPRS OUT
True side of low-power CK505-type SRC2 differential clock. Rs is integrated (No external series
resistor required).
38 SRC3C_LPRS OUT
Complement side of low-power CK505-type SRC3 differential clock. Rs is integrated (No external
series resistor required).
39 SRC3T_LPRS OUT
True side of low-power CK505-type SRC3 differential clock. Rs is integrated (No external series
resistor required).
40 VDDCORE_3.3 PWR 3.3V Power supply for 3.3V core
41 CLKREQ3# IN
Clock request input for SRC output pair 3. See the SRC, LCD, DOT Power Management Table for
details
42 CLKREQ2# IN
Clock request input for SRC output pair 2. See the SRC, LCD, DOT Power Management Table for
details
43 FSLB IN
Low threshold Frequency Select input. See Table 1: CPU Frequency Select Table and the Vih_fs and
Vil_fs specifications.
44 CPU_STOP# IN Stops all CPU clocks except those set to be free running.
45 CPUITPC_LPRS OUT
Complement side of low-power CK505-type CPUITP differential clock. Rs is integrated (No external
series resistor required). Note that this pin is NOT muxed with an SRC output.
46 CPUITPT_LPRS OUT
True side of low-power CK505-type CPUITP differential clock. Rs is integrated (No external series
resistor required).
47 CPU1C_LPRS OUT
Complement side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external
series resistor required). Note that this pin is NOT muxed with an SRC output.
48 CPU1T_LPRS OUT
True side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external series
resistor required).
49 VDDIO_CPU PWR Power supply for CPU outputs. VDD_IO = 1.05 to 3.3V +/-5%.
50 GNDCPU PWR Ground Pin for CPU Outputs
51 CPU0C_LPRS OUT
Complement side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external
series resistor required). Note that this pin is NOT muxed with an SRC output.
52 CPU0T_LPRS OUT
True side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external series
resistor required).
53 VDDCPUPLL_3.3 PWR 3.3V Power Supply for CPU PLL.
54 CK_PWRGD#/PD IN
Notifies 9UMS9001 to sample latched inputs or enter power down mode.
1 = Power down mode
Falling Edge = Sample latched inputs
0 = Normal operation
55 FSLC IN
Low threshold Frequency Select input. See Table 1: CPU Frequency Select Table and the Vih_fs and
Vil_fs specifications.
56 GNDREF PWR Ground pin for crystal oscillator circuit and REF output
P1-P3P4-P6P7-P9P10-P12P13-P15

9UMS9001AKLF

Mfr. #:
Buy 9UMS9001AKLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products CK540
Lifecycle:
New from this manufacturer.
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