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9UMS9001AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15
IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
10
General I
2
C serial interface information for the 9UMS9001
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
11
Byte 0 FS Readback, SS Enable, STOP Control Register
Bit Pin Name Description Type 0 1 Default
7
-
FSLC CPU Freq. Sel. Bit MSB
RW
Latch
6 FSLB CPU Freq. Sel. Bit LSB
RW
Latch
5 CPU_SS_EN Spread spectrum enable for CPU/SRC/PCI outputs RW SS Disabled SS Enabled 1
4 LCD_Enable Turns On LCD PLL RW Off On 1
3 SRC3_STOP SRC 3 Stop Control RW 0
2 SRC2_STOP SRC 2 Stop Control RW 0
1 SRC1_STOP SRC 1 Stop Control RW 0
0 SRC0_STOP SRC 0 Stop Control RW 0
Byte 1 LCD Quick Config and CPU Stop ControlRegister
Bit Pin Name Description Type 0 1 Default
7 CPU_ITP_STOP CPU_ITP Stop Control RW 0
6 CPU1_STOP CPU1 Stop Control RW 1
5 CPU0_STOP CPU0 Stop Control RW 1
4 LCD_SS_EN Turns on SS for LCD PLL RW Off On 1
3 LCD_SSC_SEL Select down or center SSC RW Down spread Center spread 0
2 LCD_CF2 PLL3 Quick Config Bit 2 RW 0
1 LCD_CF1 PLL3 Quick Config Bit 1 RW 0
0 LCD_CF0 PLL3 Quick Config Bit 0 RW 1
Byte 2 Output Enable and Stop Control Register
Bit Pin Name Description Type 0 1 Default
7 PCI_F2_STOP Free running PCI Stop Control RW 0
6 PCI1_STOP PCI1 Stop Control RW 1
5 PCI0_STOP PCI 0 Stop Control RW 1
4 REF_OE Output enable for REF RW Output Disabled Output Enabled 1
3 USB_OE Output enable for USB RW Output Disabled Output Enabled 1
2 PCIF2_OE Output enable for PCI2 RW Output Disabled Output Enabled 1
1 PCI1_OE Output enable for PCI1 RW Output Disabled Output Enabled 1
0 PCI0_OE Output enable for PCI0 RW Output Disabled Output Enabled 1
Byte 3 Output Enable Register
Bit Pin Name Description Type 0 1 Default
7 CPU_ITP_OE Output enable for CPU_ITP RW Output Disabled Output Enabled 1
6 CPU1_OE Output enable for CPU1 RW Output Disabled Output Enabled 1
5 CPU0_OE Output enable for CPU0 RW Output Disabled Output Enabled 1
4 Reserved Reserved RW 0
3 SRC3_OE Output enable for SRC4 RW Output Disabled Output Enabled 1
2 SRC2_OE Output enable for SRC4 RW Output Disabled Output Enabled 1
1 SRC1_OE Output enable for SRC4 RW Output Disabled Output Enabled 1
0 SRC0_OE Output enable for SRC4 RW Output Disabled Output Enabled 1
Byte 4 Output Enable and CLKREQ# Control Register
Bit Pin Name Description Type 0 1 Default
7 DOT96_OE Output enable for DOT96 RW Output Disabled Output Enabled 1
6 LCD100_OE Output enable for LCD100 RW Output Disabled Output Enabled 1
5 Reserved Reserved RW 0
4 Reserved Reserved RW 0
3 SRC3_CR SRC3 CLKREQ3# Enable RW 0
2 SRC2_CR SRC2 CLKREQ2# Enable RW 0
1 SRC1_CR SRC1 CLKREQ1# Enable RW 0
0 SRC0_CR SRC0 CLKREQ0# Enable RW 0
See Frequency Select Table
Not controlled by
CLKREQ#
Controlled by
CLKREQ#
Free Running
Stops with
PCI_STOP#
assertion
See Table 2: LCD Quick Configuration
Free Running
Stops with
CPU_STOP#
assertion
Stops with
PCI_STOP#
Assertion
Free Running
IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
12
Byte 5 Drive Strength Control Register
Bit Pin Name Description Type 0 1 Default
7 PCI_F2 Strength Sets the PCI_F2 output drive strength RW 1
6 PCI1 Strength Sets the PCI1 output drive strength RW 1
5 PCI0 Strength Sets the PCI0 output drive strength RW 1
4 48MHz Strength Sets the 48MHz output drive strength RW 1
3 REF Strength Sets the REF output drive strength RW 2 Loads 3 Loads 1
2 IO_VOUT2 IO Output Voltage Select (Most Significant Bit) RW 1
1 IO_VOUT1 IO Output Voltage Select RW 0
0 IO_VOUT0 IO Output Voltage Select (Least Significant Bit) RW 1
Byte 6 Reserved Register
Bit Pin Name Description Type 0 1 Default
7 Reserved Reserved RW 0
6 Reserved Reserved RW 0
5 Reserved Reserved RW 0
4 Reserved Reserved RW 0
3 Reserved Reserved RW 0
2 Reserved Reserved RW 0
1 Reserved Reserved RW 0
0 Reserved Reserved RW 0
Byte 7 Vendor ID/ Revision ID
Bit Pin Name Description Type 0 1 Default
7 Rev Code Bit 3 R X
6 Rev Code Bit 2 R X
5 Rev Code Bit 1 R X
4 Rev Code Bit 0 R X
3 Vendor ID bit 3 R 0
2 Vendor ID bit 2 R 0
1 Vendor ID bit 1 R 0
0 Vendor ID bit 0 R 1
Byte 8 Device ID Register
Bit Pin Name Description Type 0 1 Default
7 Device_ID3 R 0
6 Device_ID2 R 0
5 Device_ID1 R 1
4 Device_ID0 R 1
3 Reserved Reserved RW 0
2 Reserved Reserved RW 0
1 Reserved Reserved RW 0
0 Reserved Reserved RW 1
Byte 9 Test Mode Register
Bit Pin Name Description Type 0 1 Default
7 LCD_STOP LCD Stop Control RW Free Running
Stops with
PCI_STOP#
assertion
0
6 Reserved Reserved RW 0
5 Reserved Reserved RW 0
4 Test Mode Select Allows test select, ignores Test Sel input pin RW Outputs HI-Z Outputs = REF/N 0
3 Test Mode Entry Enters into test mode, ignores input pin RW Normal operation Test mode 0
2 Reserved Reserved RW 0
1 Reserved Reserved RW 0
0 PLL1_SS PLL1 Spread Spectrum Mode RW Down-spread Center-spread 0
Revision ID
Vendor ID
ICS is 0001, binary
Package ID code
Devide ID = 0011 Hex
56-pin QFN
2 Loads
See Table 3: V_IO Selection
(Default is 0.8V)
Vendor specific
1 Load
P1-P3P4-P6P7-P9P10-P12P13-P15

9UMS9001AKLF

Mfr. #:
Buy 9UMS9001AKLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products CK540
Lifecycle:
New from this manufacturer.
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