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9UMS9001AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15
IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
7
AC Electrical Characteristics - Input/Common Parameters
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Clk Stabilization T
STAB
From VDD Power-Up or de-
assertion of PD# to 1st clock
1.8 ms 1
Tdrive_SRC T
DRSRC
SRC output enable after
PCI_STOP# de-assertion
15 ns 1
Tdrive_PD# T
DRPD
Differential output enable after
PD# de-assertion
300 us 1
Tdrive_CPU T
DRSRC
CPU output enable after
CPU_STOP# de-assertion
10 ns 1
Tfall_PD# T
FALL
5ns1
Trise_PD# T
RISE
5ns1
Fall/rise time of PD#, PCI_STOP#
and CPU_STOP# inputs
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
Rising Edge Slew Rate t
SLR
Differential Measurement 1 4 V/ns 1,2
Falling Edge Slew Rate t
FLR
Differential Measurement 1 4 V/ns 1,2
Rise/Fall Time Variation t
SLVAR
Single-ended Measurement 125 ps 1
Maximum Output Voltage V
HIGH
Includes overshoot 1150 mV 1
Minimum Output Voltage V
LOW
Includes undershoot -300 mV 1
Differential Voltage Swing V
SWING
Differential Measurement 300 mV 1
Crossing Point Voltage V
XABS
Single-ended Measurement 300 550 mV 1,3,4
Crossing Point Variation V
XABSVAR
Single-ended Measurement 140 mV 1,3,5
Duty Cycle D
CYC
Differential Measurement 45 55 % 1
CPU Jitter - Cycle to Cycle CPUJ
C2C
Differential Measurement 85 ps 1
SRC Jitter - Cycle to Cycle SRCJ
C2C
Differential Measurement 125 ps 1
DOT Jitter - Cycle to Cycle DOTJ
C2C
Differential Measurement 250 ps 1
CPU[1:0] Skew CPU
SKEW10
Differential Measurement 100 ps 1
CPU[2_ITP:0] Skew CPU
SKEW20
Differential Measurement 150 ps 1
SRC[3:0] Skew SRC
SKEW
Differential Measurement 250 ps 1
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
NOTES
Long Accuracy ppm see Tperiod min-max values -300 300 ppm
1,6
33.33MHz output nominal 30.00900 ns
6
33.33MHz output spread 30.15980 ns
6
Absolute min/max period T
abs
33.33MHz output nominal/spread
29.49100
30.65980 ns
6
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.4 V 1
V
OH
@MIN = 1.0 V -33 mA 1
V
OH
@MAX = 3.135 V -33 mA 1
V
OL
@ MIN = 1.95 V 30 mA 1
V
OL
@ MAX = 0.4 V 38 mA 1
Rising Edge Slew Rate t
SLR
Measured from 0.8 to 2.0 V 1 4 V/ns 1
Falling Edge Slew Rate t
FLR
Measured from 2.0 to 0.8 V 1 4 V/ns 1
Duty Cycle d
t1
V
T
= 1.5 V 45 55 % 1
Skew t
skew
V
T
= 1.5 V 250 ps 1
Intentional PCI-PCI delay t
dela
y
V
T
= 1.5 V ps 1,9
Jitter, Cycle to cycle t
c
c-c
c
V
T
= 1.5 V 500 ps 1
0 nominal
Clock period 29.99100
Output High Current I
OH
Output Low Current I
OL
T
period
IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
8
Electrical Characteristics - USB48MHz
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
NOTES
Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1,2
Clock period T
p
eriod
48.00MHz output nominal 20.83125 20.83542 ns 2
Absolute min/max period T
abs
48.00MHz output nominal 20.48130 21.18540 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.4 V 1
V
OH
@MIN = 1.0 V -29 mA 1
V
OH
@MAX = 3.135 V -23 mA 1
V
OL
@ MIN = 1.95 V 29 mA 1
V
OL
@ MAX = 0.4 V 27 mA 1
Rising Edge Slew Rate t
SLR
Measured from 0.8 to 2.0 V 1 2 V/ns 1
Falling Edge Slew Rate t
FLR
Measured from 2.0 to 0.8 V 1 2 V/ns 1
Duty Cycle d
t1
V
T
= 1.5 V 45 55 % 1
Jitter, Cycle to cycle t
c
c-c
c
V
T
= 1.5 V 350 ps 1
Output High Current I
OH
I
OL
Output Low Current
Electrical Characteristics - SMBus Interface
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
SMBus Voltage V
DD
2.7 5.5 V 1
Low-level Output Voltage V
OLSM B
@ I
PULLUP
0.4 V 1
Current sinking at
V
OLSMB
= 0.4 V
I
PULLUP
SMB Data Pin 4 mA 1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300 ns 1
Maximum SMBus Operating
Frequency
F
SMBUS
Block Mode 100 kHz 1
IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
9
Notes on Electrical Characteristics:
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing centered around differential zero
3
Vxabs is defined as the voltage where CLK = CLK#
4
Only applies to the differential rising edge (CLK rising and CLK# falling)
6
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
9
See PCI Clock-to-Clock Delay Figure
5
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets
CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate
calculations
8
Maximum input voltage is not to exceed maximum VDD
7
Operation under these conditions is neither implied, nor guaranteed.
Electrical Characteristics - REF-14.318MHz
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2
Clock period T
p
eriod
14.318MHz output nominal 69.8203 69.8622 ns 2
Absolute min/max period T
abs
14.318MHz output nominal 69.8203 70.86224 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.4 V 1
Output High Current I
OH
V
OH
@MIN = 1.0 V,
V
OH
@MAX = 3.135 V
-33 -33 mA 1
Output Low Current I
OL
V
OL
@MIN = 1.95 V,
V
OL
@MAX = 0.4 V
30 38 mA 1
Rising Edge Slew Rate t
SLR
Measured from 0.8 to 2.0 V 1 4 V/ns 1
Falling Edge Slew Rate t
FLR
Measured from 2.0 to 0.8 V 1 4 V/ns 1
Duty Cycle d
t1
V
T
= 1.5 V 45 55 % 1
Jitter t
jcyc-cyc
V
T
= 1.5 V 1000 ps 1
P1-P3P4-P6P7-P9P10-P12P13-P15

9UMS9001AKLF

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IDT
Description:
Clock Generators & Support Products CK540
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