NB6L295MMNG Datasheet NB6L295MMNTXG, NB6L295MMNG | P7-P9

NB6L295M

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Serial Data Interface Programming

The NB6L295M is programmed by loading the 11−Bit SHIFT REGISTER using the SCLK, SDATA and SLOAD inputs.

The 11 SDATA bits are 1 PSEL bit, 1 MSEL bit and 9 delay value data bitsD[8:0]. A separate 11−bit load cycle is required to

program the delay data value of each channel, PD0 and PD1. For example, at powerup two load cycles will be needed to initially

set PD0 and PD1; Dual Mode Operation as shown in Figures 3 and 4 and Extended Mode Operation as shown in Figures 5

and 6.

DUAL MODE OPERATIONS

PD0 Programmable Delay

Control

Bits

Value

PD1 Programmable Delay

Control

Bits

Value

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 1

D8 D7 D6 D5 D4 D3 D2 D1 D0 MSEL PSEL

Bit

Name

D8 D7 D6 D5 D4 D3 D2 D1 D0 MSEL PSEL

Bit

Name

(MSB) (LSB)

Name

(MSB) (LSB)

Name

Figure 3. PDO Shift Register Figure 4. PD1 Shift Register

EXTENDED MODE OPERATIONS

PD0 Programmable Delay

Control

Bits

Value

PD1 Programmable Delay

Control

Bits

Value

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1

D8 D7 D6 D5 D4 D3 D2 D1 D0 MSEL PSEL

Bit

Name

D8 D7 D6 D5 D4 D3 D2 D1 D0 MSEL PSEL

Bit

Name

(MSB) (LSB)

Name

(MSB) (LSB)

Name

Figure 5. PDO Shift Register Figure 6. PD1 Shift Register

Refer to Table 6, Channel and Mode Select BIT Functions. In a load cycle, the 11−Bit Shift Register least significant bit

(clocked in first) is PSEL and will determine which channel delay buffer, either PDO (LOW) or PD1 (HIGH), will latch the

delay data value D[8:0]. The MSEL BIT determines the Delay Mode. When set LOW, the Dual Delay Mode is selected and

the device uses both channels independently. A pulse edge entering IN0/IN0

is delayed according to the values in PD0 and exits

from Q0/Q0

. An input signal pulse edge entering IN1/IN1 is delayed according to the values in PD1 and exits from Q1/Q1.

When MSEL is set HIGH, the Extended Delay Mode is selected and an input signal pulse edge enters IN0 and IN0

and flows

through PD0 and is extended through PD1 to exit at Q1 and Q1

. The most significant 9−bits, D[8:0] are delay value data for

both channels. See Figure 7.

Table 6. CHANNEL AND MODE SELECT BIT FUNCTIONS

BIT Name Function

PSEL

0 Loads Data to PD0

1 Loads Data to PD1

MSEL

0 Selects Dual Programmable Delay Paths, 3.1 ns to 8.8 ns Delay Range for Each Path

1 Selects Extended Delay Path from IN0/IN0 to Q1/Q1, 6.0 ns to 17.2 ns Delay Range; Disables Q0/Q0 Outputs,

Q0−LOW, Q0

−HIGH.

D[8:0] Select one of 512 Delay Values

NB6L295M

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MSEL

PSEL

Figure 7. Serial Data Interface, Shift Register, Data Latch, Programmable Delay Channels

Load Cycle Required for Each Channel

PD1 LatchPD0 Latch

PD0 Delay PD1 Delay

SLOAD

Q1/Q1

Q0/Q0

SDATA

SCLK

11−Bit Shift Register

MSEL

Serial Data Interface Loading

Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by

using the SCLK input pin and latching the data with the SLOAD input pin. The 11−bit SHIFT REGISTER shifts once per rising

edge of the SCLK input. The serial input SDIN must meet setup and hold timing as specified in the AC Characteristics section

of this document for each bit and clock pulse. The SLOAD line loads the value of the shift register on a LOW−to−HIGH edge

transition (transparent state) into a data Latch register and latches the data with a subsequent HIGH−to−LOW edge transition.

Further changes in SDIN or SCLK are not recognized by the latched register. The internal multiplexer states are set by the PSEL

and MSEL bits in the SHIFT register. Figure 6 shows the timing diagram of a typical load sequence.

Input EN

should be LOW (enabled) prior to SDI programming, then pulled HIGH (disabled) during programming. After

programming, the EN

should be returned LOW (enabled) for functional delay operation.

The disabling of EN

(HIGH) forces Qx LOW and Qx HIGH and is included during programming to prevent (or mask out)

any potential run pulses or extended pulses which might occur in the internal delay gates programming switching, but it is not

required for programming.

D4 D8D7

Figure 8. SDI Programming Cycle Timing Diagram (Load Cycle 1 of 2)

SDIN

SCLK

SLOAD

MSB

PSEL MSEL D0 D1 D2 D3 D5 D6

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10

SDIN to

SCLK

SDIN to SCLK

SCLK to SLOAD

EN to SDIN

LSB

to SLOAD

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Table 7 shows theoretical values of delay capabilities in both the Dual Delay Mode and in the Extended Delay Modes of

operation.

Table 7. EXAMPLES OF THEORETICAL DELAY VALUES FOR PD0 AND PD1 IN DUAL MODE

INPUTS: IN0/IN0, IN1/IN1, OUTPUTS: Q0/Q0, Q1, Q1

Dual Mode

PD0 Delay* (ps) PD1 Delay* (ps)

PD1 D[8:0] (Decimal) PD0 D[8:0] (Decimal) MSEL

000000000 (0) 000000000 (0) 0 0 0

000000000 (0) 000000001 (1) 0 11 0

000000000 (0) 000000010 (2) 0 22 0

000000000 (0) 000000011 (3) 0 33 0

000000000 (0) 000000100 (4) 0 44 0

000000000 (0) 000000101 (5) 0 55 0

000000000 (0) 000000110 (6) 0 66 0

000000000 (0) 000000111 (7) 0 77 0

000000000 (0) 000001000 (8) 0 88 0

•

000000000 (0) 000010000 (16) 0 176 0

000000000 (0) 000100000 (32) 0 352 0

000000000 (0) 001000000 (64) 0 704 0

000000000 (0) 111111101 (509) 0 5599 0

000000000 (0) 111111110 (510) 0 5610 0

000000000 (0) 111111111 (511) 0 5621 0

*Fixed minimum delay not included

Table 8. EXAMPLES OF THEORETICAL DELAY VALUES FOR PD0 AND PD1 IN EXTENDED MODE

INPUTS: IN0/IN0, IN1/IN1, OUTPUTS: Q0/Q0, Q1, Q1

Extended Delay Mode

PD0* (ps) PD1* (ps) Total Delay* (ps)

PD1 D[8:0]

(Decimal)

PD0 D[8:0]

(Decimal)

MSEL

000000000 (0) 000000000 (0) 1 0 0 0

000000000 (0) 000000001 (1) 1 0 11 11

000000000 (0) 000000010 (2) 1 0 22 22

000000000 (0) 000000011 (3) 1 0 33 33

•

000000000 (0) 111111101 (509) 1 0 5599 5599

000000000 (0) 111111110 (510) 1 0 5610 5610

000000000 (0) 111111111 (511) 1 0 5621 5621

000000001 (1) 111111111 (511) 1 11 5621 5632

000000010 (2) 111111111 (511) 1 22 5621 5643

•

111111100 (508) 111111111 (511) 1 5588 5621 11209

111111101 (509) 111111111 (511) 1 5599 5621 11220

111111110 (510) 111111111 (511) 1 5610 5621 11231

111111111 (511) 111111111 (511) 1 5621 5621 11242

*Fixed minimum delay not included

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

NB6L295MMNG

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Delay Lines / Timing Elements CML DUAL PROG DELAY

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NB6L295MMNG

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