25AA02E48/25AA02E64
DS20002123F-page 10 2008-2016 Microchip Technology Inc.
2.5 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. See Figure 2-6 for the
RDSR timing sequence. The STATUS register may be
read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2: STATUS REGISTER
The Write-In-Process (WIP) bit indicates whether the
25AA02EXX is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is shown in Figure 2-7. These bits are nonvolatile and
are described in more detail in Table 2-3.
FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)
7 654 3 2 1 0
– –––W/RW/R R R
X XXXBP1 BP0 WEL WIP
W/R = writable/readable. R = read-only.
SO
SI
CS
9101112131415
11000000
7654 210
Instruction
Data from STATUS register
High-Impedance
SCK
0 2345671
8
3
