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25AA02E48T-I/SN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
2008-2016 Microchip Technology Inc. DS20002123F-page 7
25AA02E48/25AA02E64
BLOCK DIAGRAM
FIGURE 2-1: READ SEQUENCE
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control
Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
TABLE 2-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ 0000 x011 Read data from memory array beginning at selected address
WRITE 0000 x010 Write data to memory array beginning at selected address
WRDI 0000 x100 Reset the write enable latch (disable write operations)
WREN 0000 x110 Set the write enable latch (enable write operations)
RDSR 0000 x101 Read STATUS register
WRSR 0000 x001 Write STATUS register
x = don’t care
SO
SI
SCK
CS
0 2345678910111
01000001A
7
A
6
A
5
A
4
A
1
A
0
76543210
Data Out
High-Impedance
A
3
A
2
Address Byte
12
13 14
15 16
17
18
19
20
21 22 23
Instruction
25AA02E48/25AA02E64
DS20002123F-page 8 2008-2016 Microchip Technology Inc.
FIGURE 2-2: BYTE WRITE SEQUENCE
FIGURE 2-3: PAGE WRITE SEQUENCE
SO
SI
CS
0 2345678910111
00000001 A
6
A
5
A
4
A
1
A
3
A
2
Address Byte
12
13 14
15 16
17
18
19
20
21 22 23
Instruction
Data Byte
A
0
6
7
5
43
2
1
0
High-Impedance
Twc
SCK
A
7
SI
CS
91011
00000001
76543210
Data Byte 1
SCK
0 2345671
8
SI
CS
33 34 35 38 39
76543210
Data Byte n (16 max)
SCK
24 26 27 28 29 30 3125
32
76543210
Data Byte 3
76543210
Data Byte 2
36 37
Instruction
Address Byte
A
7
A
6
A
5
A
4
A
3
A
1
A
0
A
2
12
13
14 15 16 17 18
19
20 21 22 23
2008-2016 Microchip Technology Inc. DS20002123F-page 9
25AA02E48/25AA02E64
2.4 Write Enable (WREN) and Write
Disable (WRDI)
The 25AA02EXX contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
•WP
pin is brought low
FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)
FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 01
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 0
0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

25AA02E48T-I/SN

Mfr. #:
Buy 25AA02E48T-I/SN
Manufacturer:
Microchip Technology
Description:
EEPROM 2K, 256x8, 1.8V MAC Addressable
Lifecycle:
New from this manufacturer.
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