13
LTC1143/LTC1143L
LTC1143L-ADJ
Shutdown Considerations
Pins 2 and 10 on the LTC1143 and LTC1143L shut down
their respective sections when pulled high. They require
CMOS logic level signals with t
r
, t
f
< 1µs and must never
be floated. The LTC1143L-ADJ gives up the pin-controlled
shutdown function in order to gain feedback pins for
programming the output voltages.
OUTPUT CURRENT (A)
0.01
EFFICIENCY (%)
90
95
1
LTC1143 • F05
85
80
0.03
0.1
0.3
3
100
GATE CHARGE
1
⁄
2
LTC1143 I
Q
I
2
R
SCHOTTKY
DIODE
Figure 5. Efficiency Loss
8% as the load current increases from 0.5A to 2A. If
Schotky diode losses routinely exceed 5% consider
using the synchronously switched LTC1142 series.
Figure 5 shows how the efficiency losses in one section of
a typical LTC1143 series regulator end up being appor-
tioned. The gate charge loss is responsible for the majority
of the efficiency lost in the midcurrent region. If Burst
Mode operation was not employed at low currents, the
gate charge loss alone would cause efficiency to drop to
unacceptable levels. With Burst Mode operation, the DC
supply current represents the lone (and unavoidable) loss
component, which continues to become a higher percent-
age as output current is reduced. As expected, the I
2
R
losses and Schottky diode loss dominate at high load
currents.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, MOSFET switching losses and inductor core losses,
generally account for less than 2% total additional loss.
drawn from V
IN
, the resulting loss increases with
input voltage. For V
IN
= 10V the DC bias losses are
generally less than 1% for load currents over 30mA.
However at very low load currents the DC bias current
accounts for nearly all of the loss.
2) MOSFET gate charge current results from switching
the gate capacitance of the power MOSFET. Each time
a MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from V
IN
to ground. The
resulting dQ/dt is a current out of V
IN
that is typically
much larger than the DC supply current. In continuous
mode, I
GATECHG
= ƒ(Q
P
). The typical gate charge for
a 0.05Ω P-channel power MOSFET is 40nC. This
results in I
GATECHG
= 4mA in 100kHz continuous opera-
tion, for a 2% to 3% typical midcurrent loss with
V
IN
= 10V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it
argues against using a larger MOSFET than necessary
to control I
2
R losses, since overkill can cost efficiency
as well as money!
3) I
2
R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continuous
mode the average output current flows through L and
R
SENSE
, but is “chopped” between the P-channel
MOSFET and Schottky diode. The MOSFET R
DS(ON)
multi-
plied by the P-channel duty cycle can be summed with
the resistances of L and R
SENSE
to obtain I
2
R losses.
For example, if the R
DS(ON)
= 0.1Ω, R
L
= 0.15Ω, and
R
SENSE
= 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 10% as the output
current increases from 0.5A to 2A. I
2
R losses cause the
efficiency to roll off at high output currents.
4) The Schottky diode is a major source of power loss at
high currents and gets worse at high input voltages.
The diode loss is calculated by multiplying the forward
voltage drop times the Schottky diode duty cycle
multiplied by the load current. For example, assuming
a duty cycle of 50% with a Schottky diode forward
voltage drop of 0.4V, the loss increases from 0.5% to
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