16
LTC1143/LTC1143L
LTC1143L-ADJ
APPLICATIONS INFORMATION
WUU
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5) Is the V
IN
decoupling capacitor (1µF, 0.1µF) con-
nected closely between
Pin 13 (5) and GND Pin 3
(11)? This capacitor carries the MOSFET driver peak
currents.
6) For the LTC1143 and LTC1143L, are the SHUT-
DOWN Pins 2 and 10 actively pulled to ground
during normal operation? Both SHUTDOWN pins are
high impedance and must not be allowed to float. Both
pins can be driven by the same external signal if
needed.
7) For the LTC1143L-ADJ, are the V
FB
Pins 2 and 10
decoupled with 100pF as close to the device as
possible? The V
FB
line is sensitive to noise pickup and
should be kept away from the P-channel MOSFET.
Figure 9. LTC1143 Layout Diagram (see Board Layout Checklist)
+ +
C
OUT5
C
IN3
V
OUT5
+
–
R
SENSE5
R
SENSE3
L1
L2
P-CH
D1
D2
1k
*MUST BE LOCATED CLOSE TO LTC1143
SHUTDOWN
(3.3V OUTPUT)
C
T5
P-CH
C
IN5
C
OUT3
V
IN3
V
IN5
BOLD LINES INDICATE HIGH CURRENT PATHS
SHUTDOWN
(5V OUTPUT)
+
V
OUT3
+
–
+
–
1000pF*
1000pF*
0.0033µF
1k
C
T3
0.0033µF
+
–
0.22µF*
0.22µF*
SENSE
+
3
SHUTDOWN 3
P-DRIVES3
C
T5
I
TH5
SENSE
–
5
SENSE
–
3
I
TH3
C
T3
P-DRIVES5
SHUTDOWN 5
SENSE
+
5
LTC1143
GND5
V
IN5
V
IN5
V
IN3
V
IN3
GND3
+
1143 F09
