7
LTC1143/LTC1143L
LTC1143L-ADJ
The LTC1143 series consists of two individual regulator
blocks, each using current mode, constant off-time archi-
tectures to switch an external power MOSFET. The two
LTC1143/LTC1143L regulators are internally set for 3.3V
and 5V, while the two LTC1143L-ADJ regulators have
externally programmable output voltages. Operating fre-
quency is individually set on each section by external
capacitors at the timing capacitor Pins 6 and 14.
The output voltage is sensed by voltage comparator V and
gain block G, which compare the divided output voltage
with a reference voltage of 1.25V. To optimize efficiency,
the LTC1143 series automatically switches between two
modes of operation, burst and continuous. The voltage
comparator is the primary control element when the
device is in Burst Mode operation, while the gain block
controls the output voltage in continuous mode.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 1 (9) and
16 (8) connected across an external shunt in series with
the inductor. When the voltage across the shunt reaches
its threshold value, the P-drive output is switched to V
IN
,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 14 (6) is now allowed to discharge at a
rate determined by the off-time controller. The discharge
current is made proportional to the feedback voltage to
model the inductor current, which decays at a rate that is
also proportional to the output voltage.
When the voltage on the timing capacitor has discharged
past V
TH1
, comparator T trips, setting the flip-flop. This
causes the P-drive output to go low, turning the P-channel
MOSFET back on. The cycle then repeats.
As the load current increases, the output voltage
decreases slightly. This causes the output of the gain
stage [Pin 15 (7)] to increase the current comparator
threshold, thus tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel
MOSFET is held off by comparator V and the timing
capacitor continues to discharge below V
TH1
. When the
timing capacitor discharges past V
TH2
, voltage compara-
tor S trips, causing the internal sleep line to go low.
OPERATION
U
Refer to Functional Diagram and Figure 1.
+
+
REFERENCE
4(12)
P-DRIVE
GROUND
V
IN
+
V
+
C
25mV TO 150mV
+
1(9)
V
OS
2(10)
SHUTDOWN
(LTC1143/LTC1143L)
V
FB
(LTC1143L-ADJ)
100k
X
X
16(8)
1.25V
5pF
G
15(7)
I
TH
Q
R
S
V
IN
SENSE
OFF-TIME
CONTROL
14(6)
13k
+
S
SLEEP
V
TH1
C
T
T
SENSE
SENSE
+
V
TH2
1143 FD
13(5)
3(11)
Only one regulator block shown. Connections shown for LT1143/LTC1143L; changes create LTC1143L-ADJ
FUNCTIONAL DIAGRA
UU
W
8
LTC1143/LTC1143L
LTC1143L-ADJ
OPERATION
U
Refer to Functional Diagram and Figure 1
The circuit now enters sleep mode with the power MOSFET
turned off. In sleep mode a majority of the circuitry is
turned off, dropping the quiescent current from 1.6mA to
160µA (for one regulator block). The load current is now
being supplied from the output capacitor. When the output
voltage has dropped by the amount of hysteresis in
comparator V, the P-channel MOSFET is again turned on
and the process repeats.
To avoid the operation of the current loop interfering with
Burst Mode operation, a built-in offset (V
OS
) is incorpo-
rated in the gain stage. This prevents the current compara-
tor threshold from increasing until the output voltage has
dropped below a minimum threshold.
Using constant off-time architecture the operating fre-
quency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-time
controller increases the C
T
discharge current as V
IN
drops
below V
OUT
+ 1.5V. In dropout the P-channel MOSFET is
turned on continuously (100% duty cycle), providing
extremely low dropout operation.
For Figure 1 applications with V
OUT
below 2V, or when
R
SENSE
is moved to ground, the current sense comparator
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, the off-time
increases approximately 40%, requiring the use of a
smaller timing capacitor C
T
.
R
SENSE
Selection for Output Current
R
SENSE
is chosen based on the required output current.
The LTC1143 series current comparators have a threshold
range that extends from a minimum of 25mV/R
SENSE
to a
maximum of 150mV/R
SENSE
. The current comparator
threshold sets the peak of the inductor ripple current,
yielding a maximum output current I
MAX
equal to the peak
value less half the peak-to-peak ripple current.
For proper
Burst Mode operation, I
RIPPLE(P-P)
must be less than or
equal to the minimum current comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
I
RIPPLE(P-P)
= 25mV/R
SENSE
. (See C
T
and L Selection for
Operating Frequency). Solving for R
SENSE
and allowing a
margin for variations in the LTC1143 series and external
component values yields:
R
SENSE
=
100mV
I
MAX
A graph for selecting R
SENSE
versus maximum output
current is given in Figure 2.
The basic LTC1143L-ADJ application circuit is shown in
Figure 1. The LTC1143 and LTC1143L are similar but omit
the external resistive V
OUT
dividers (see Figures 10 and
13). External component selection is driven by the load
requirement and begins with V
OUT
and the selection of
R
SENSE
. Once R
SENSE
is known, C
T
and L can be chosen.
Next, the power MOSFET and D1 are selected. Finally, C
IN
and C
OUT
are selected and the loop is compensated. Since
the two regulator sections are identical, the process of
component selection is the same for both sections. The
circuit shown in Figure 1 can be configured for operation
up to an input voltage of 16V.
Output Voltage Selection
The LTC1143/LTC1143L output voltages are internally set
to 3.3V and 5V. The LTC1143L-ADJ requires an external
resistive divider from V
OUT
to V
FB
on each section as
shown in Figure 1. The regulated LTC1143L-ADJ output
voltages are given by:
V
R
R
V
R
R
OUT
OUT
1
2
125 1
2
1
125 1
4
3
=+
=+
.
.
To prevent stray pickup, a 100pF capacitor is suggested
across R1 and R3 located close to the LTC1143L-ADJ.
APPLICATIONS INFORMATION
WUU
U
9
LTC1143/LTC1143L
LTC1143L-ADJ
APPLICATIONS INFORMATION
WUU
U
MAXIMUM OUTPUT CURRENT (A)
0
R
SENSE
()
0.20
0.15
0.10
0.05
0
4
1143 F02
1
2
3
5
Figure 2. Selecting R
SENSE
The load current below which Burst Mode operation
commences, I
BURST
, and the peak short circuit current,
I
SC(PK)
, both track I
MAX
. Once R
SENSE
has been chosen,
I
BURST
and I
SC(PK)
can be predicted from the following:
I
BURST
15mV
R
SENSE
I
SC(PK)
=
150mV
R
SENSE
The LTC1143 series automatically extends t
OFF
during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
I
SC(AVG)
to be reduced to approximately I
MAX
.
L and C
T
Selection for Operating Frequency
Each regulator section of the LTC1143 series uses a
constant off-time architecture with t
OFF
determined by an
external timing capacitor C
T
. Each time the P-channel
MOSFET switch turns on the voltage on C
T
is reset to
approximately 3.3V. During the off-time, C
T
is discharged
by a current that is proportional to V
OUT
. The voltage on C
T
is analogous to the current in inductor L, which likewise
decays at a rate proportional to V
OUT
. Thus the inductor
value must track the timing capacitor value.
The value of C
T
is calculated from the desired continuous
mode operating frequency:
C
f
VV
VV
T
IN OUT
IN D
=
+
1
13 10
4
.
where V
D
is the drop across the diode.
A graph for selecting C
T
versus frequency including the
effects of input voltage is given in Figure 3.
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency of the circuit in Figure 1 is given by:
f
t
V
V
OFF
OUT
IN
≈−
1
1
where:
tC
V
V
OFF T
REG
OUT
=
13 10
4
.
V
REG
is the desired output voltage (i.e., 5V, 3.3V). V
OUT
is the measured output voltage. Thus V
REG
/V
OUT
= 1 in
regulation.
Note that as V
IN
decreases, the frequency decreases.
When the input-to-output voltage differential drops below
1.5V for a particular section, the LTC1143 series reduces
t
OFF
in that section by increasing the discharge current in
C
T
. This prevents audible operation prior to dropout.
FREQUENCY (kHz)
0
CAPACITANCE (pF)
50
100
150 200
LTC1143 F03
250
1000
800
600
400
200
0
300
V
IN
= 12V
V
IN
= 10V
V
IN
= 7V
V
SENSE
= V
OUT
= 5V
Figure 3. Timing Capacitor Value

LTC1143LCS#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2x Hi Eff SO-16 Buck Sw Reg Cntrs
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New from this manufacturer.
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