CY7C1046D
Document Number: 38-05705 Rev. *G Page 4 of 16
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Supply voltage on
V
CC
to relative GND
[1]
................................–0.5 V to +6.0 V
DC voltage applied to outputs
in high Z state
[1]
..................................–0.5 V to V
CC
+ 0.5 V
DC input voltage
[1]
.............................–0.5 V to V
CC
+ 0.5 V
Current into outputs (LOW) ........................................20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ..........................> 2001 V
Latch up current .....................................................> 200 mA
Operating Range
Range Ambient Temperature V
CC
Industrial –40 C to +85 C 4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
-10
Unit
Min Max
V
OH
Output HIGH voltage V
CC
= Min, I
OH
= –4.0 mA 2.4 V
V
CC
= Max, I
OH
= –0.1 mA 3.4
[2]
V
OL
Output LOW voltage V
CC
= Min, I
OL
= 8.0 mA 0.4 V
V
IH
Input HIGH voltage 2.0 V
CC
+ 0.5 V
V
IL
Input LOW voltage
[1]
–0.5 0.8 V
I
IX
Input leakage current GND < V
IN
< V
CC
–1 +1 A
I
OZ
Output leakage current GND < V
OUT
< V
CC
, output disabled –1 +1 A
I
CC
V
CC
operating supply current V
CC
= Max, f = f
MAX
= 1/t
RC
100 MHz 90 mA
83 MHz 80
66 MHz 70
40 MHz 60
I
SB1
Automatic CE Power-Down
Current – TTL inputs
Max V
CC
, CE > V
IH
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
–20mA
I
SB2
Automatic CE Power-Down
Current – CMOS inputs
Max V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V, or V
IN
< 0.3 V, f = 0
–10mA
Notes
1. V
IL
(min) = –2.0 V and V
IH
(max) = V
CC
+ 2 V for pulse durations of less than 20 ns.
2. Please note that the maximum V
OH
limit does not exceed minimum CMOS V
IH
of 3.5V. If you are interfacing this SRAM with 5V legacy processors that require a
minimum V
IH
of 3.5V, please refer to Application Note AN6081 for technical details and options you may consider.
CY7C1046D
Document Number: 38-05705 Rev. *G Page 5 of 16
Capacitance
Parameter
[3]
Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25 C, f = 1 MHz, V
CC
= 5.0 V 8 pF
C
OUT
I/O capacitance 8pF
Thermal Resistance
Parameter
[3]
Description Test Conditions SOJ Package Unit
JA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
53.44 C/W
JC
Thermal resistance
(junction to case)
38.25 C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
[4]
90%V
CC
10%V
CC
3 V
GND
90%
10%
ALL INPUT PULSES
5 V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(c)
OUTPUT
R1 481
R2
255
167
Equivalent to: THÉVENIN EQUIVALENT
1.73 V
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
OUTPUT
Z = 50
50
1.5 V
(a)
Rise Time:1 V/ns
Fall Time: 1 V/ns
(b)
High Z Characteristics:
CY7C1046D
Document Number: 38-05705 Rev. *G Page 6 of 16
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions
[5]
Min Max Unit
V
DR
V
CC
for data retention 2.0 V
I
CCDR
Data retention current V
CC
= V
DR
= 2.0 V, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V or V
IN
< 0.3 V
–10mA
t
CDR
[6]
Chip deselect to data retention
time
0–ns
t
R
[7]
Operation recovery time t
RC
–ns
Data Retention Waveform
Figure 3. Data Retention Waveform
4.5 V4.5 V
t
CDR
V
DR
> 2 V
DATA RETENTION MODE
t
R
CE
V
CC
Notes
5. No inputs may exceed V
CC
+ 0.3 V.
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 50 s or stable at V
CC(min)
> 50 s.

CY7C1046D-10VXI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4Mb 10ns 1M x 4 Fast Async SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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