CY7C1046D
Document Number: 38-05705 Rev. *G Page 7 of 16
Switching Characteristics
Over the Operating Range
Parameter
[8]
Description
7C1046D-10
Unit
Min Max
Read Cycle
t
power
V
CC
(typical) to the first access
[9]
100 s
t
RC
Read cycle time 10 ns
t
AA
Address to data valid 10 ns
t
OHA
Data hold from address change 3 ns
t
ACE
CE LOW to data valid 10 ns
t
DOE
OE LOW to data valid 5 ns
t
LZOE
OE LOW to low Z
[11]
0 ns
t
HZOE
OE HIGH to high Z
[10, 11]
5 ns
t
LZCE
CE LOW to low Z
[11]
3 ns
t
HZCE
CE HIGH to high Z
[10, 11]
5 ns
t
PU
CE LOW to power-up 0 ns
t
PD
CE HIGH to power-down 10 ns
Write Cycle
[12, 13]
t
WC
Write cycle time 10 ns
t
SCE
CE LOW to write end 7 ns
t
AW
Address set-up to write end 7 ns
t
HA
Address hold from write end 0 ns
t
SA
Address set-up to write start 0 ns
t
PWE
WE pulse width 7 ns
t
SD
Data set-up to write end 6 ns
t
HD
Data hold from write end 0 ns
t
LZWE
WE HIGH to low Z
[11]
3 ns
t
HZWE
WE LOW to high Z
[10, 11]
5 ns
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
9. t
POWER
gives the minimum amount of time that the power supply should be at stable, typical V
CC
values until the first memory access can be performed.
10. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads.Transition is measured when the outputs enter a high impedance
state.
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
12. The internal write time of the memory is defined by the overlap of CE
LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
13. The minimum write cycle time for Write Cycle no. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
CY7C1046D
Document Number: 38-05705 Rev. *G Page 8 of 16
Switching Waveforms
Figure 4. Read Cycle No. 1
[14, 15]
Figure 5. Read Cycle No. 2 (OE Controlled)
[15, 16]
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
I
CC
I
SB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
Notes
14. Device is continuously selected. OE
, CE = V
IL
.
15. WE
is HIGH for read cycle.
16. Address valid prior to or coincident with CE
transition LOW.
CY7C1046D
Document Number: 38-05705 Rev. *G Page 9 of 16
Figure 6. Write Cycle No. 1 (CE Controlled)
[17, 18]
Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[17, 18]
Switching Waveforms (continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
ADDRESS
WE
DATA I/O
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 19
Notes
17. Data I/O is high impedance if OE
= V
IH
.
18. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
19. During this period the I/Os are in the output state and input signals should not be applied.

CY7C1046D-10VXI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4Mb 10ns 1M x 4 Fast Async SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet